Abstract: A mobile terminal and a method for transmitting a message thereof are provided. The method for transmitting a message in a mobile terminal including at least two communication units capable of communicating with different communication networks, includes, identifying circuits connected through the at least two communication units when at least two identification information of other mobile terminals to which the message is to be transmitted is input, and simultaneously transmitting the message to the at least two other mobile terminals according to the identification information through the identified circuits. Through the method, a message can be simultaneously transmitted to a plurality of other mobile terminals using characteristics of a multi-standby mobile terminal. In addition, the message transmission method can reduce a time required to transmit a message.

Abstract: A fail-safe method and apparatus for high voltage parts in a hybrid vehicle is provided. In the fail-safe method, it is determined whether or not a high voltage main relay is turned off. Here, when the high voltage main relay is turned off, a voltage is charged into a direct current (DC) link using a counter electromotive force generated in a motor generator linked with a revolution of an engine. Voltage control is performed such that the voltage of the DC link is uniformly maintained using an inverter for the motor generator.

Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure.

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

Abstract: In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

Abstract: Disclosed is an inverter control system and method for an eco-friendly vehicle, by which overall improvements can be obtained in terms of switching loss, electromagnetic performance, noise-vibration-harshness (NVH) performance, control stability, and so forth, when compared to a conventional case in which one fixed switching frequency and one fixed sampling frequency are used over the entire operation area. To this end, the inverter control method for an eco-friendly vehicle which generates a pulse width modulation (PWM) signal according to a switching frequency and a sampling frequency and controls ON/OFF driving of a switching element, in which a controller changes and sets the switching frequency according to a current motor speed, changes and sets a sampling frequency according to the switching frequency, and controls on/off driving of a switching element according to the switching frequency corresponding to the motor speed and the sampling frequency.

Abstract: Provided is an inverter control system and method for an eco-friendly vehicle, by which overall improvements can be obtained in terms of switching loss, electromagnetic performance, noise-vibration-harshness (NVH) performance, control stability, and so forth, when compared to a conventional case in which one fixed switching frequency and one fixed sampling frequency are used over the entire operation area. To this end, the inverter control method for an eco-friendly vehicle which generates a pulse width modulation (PWM) signal according to a switching frequency and a sampling frequency and controls ON/OFF driving of a switching element, in which a controller changes and sets the switching frequency according to a current motor speed, changes and sets a sampling frequency according to the switching frequency, and controls on/off driving of a switching element according to the switching frequency corresponding to the motor speed and the sampling frequency.

Abstract: A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

Abstract: The present invention provides a method for compensating nonlinearity of a resolver to control a motor in hybrid and fuel cell vehicles, thereby stably controlling the motor current during high-torque and high-speed operation. In preferred aspects, the present invention provides a method for compensating nonlinearity of a resolver to control a motor in hybrid and fuel cell vehicles, the method including collecting resolver position data; determining whether to perform resolver position correction in the corresponding vehicle; and compensating nonlinearity of the resolver based on the collected resolver position data, if it is determined that the resolver position correction is not performed.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract: Disclosed is a method for controlling a permanent magnet synchronous motor to maximize use of voltages of a battery by voltage phase control within weak magnetic flux area and to achieve compensation for a torque error through a torque compensator when driving the permanent magnet synchronous motor for hybrid vehicles. In particular, the method controls a permanent magnet synchronous motor so that voltage use can be maximized in a weak magnetic flux area by using voltage near maximum voltage through voltage phase control utilizing magnetic flux-based map data receiving a torque command and motor speed/batter output voltage as inputs and torque error can be compensated using a torque compensation filter when a motor constant is changed in the weak magnetic flux by a circumstance parameter, when the permanent magnet synchronous motor mounted in a hybrid vehicle and an electric vehicle is driven.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

Abstract: A soldering structure using Zn includes a bonding layer which contains Zn; and a lead-free solder which bonds and reacts to the bonding layer. The bonding layer can be a Zn alloy layer or a multilayer including a Zn layer. Accordingly, the characteristics of the soldering structure can be improved by involving the high reactive Zn to the interfacial reaction of the soldering.

Abstract: The present invention provides a motor drive system for a hybrid vehicle and a method for controlling the same in the event of a failure in a voltage converter, in which high voltage stored in a DC-link capacitor is discharged to a 12V electrical load through a DC-DC converter, of which the output voltage is increased.

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

Abstract: A method for controlling a cooling system for controlling a power converter of a hybrid electric vehicle includes: estimating the temperature of a power converter at the time of a CAN communication error as a current temperature of the power converter and controlling a cooling system at a cooling rate based on the estimated temperature; and controlling the cooling rate of the cooling system depending on whether an output of the power converter is greater than a reference value. According to the method, the cooling system can be more effectively controlled.

Abstract: In an embodiment, a method of forming a bonded structure is provided. The method may include forming at least one first under bump metallurgy (UBM) structure on a first substrate, forming a first gold layer on the at least one first under bump metallurgy structure; forming a tin layer on the first gold layer, forming an indium layer on the tin layer, forming an inhibition layer configured to inhibit oxygen penetration on the indium layer, and forming at least one second under bump metallurgy structure on a second substrate, forming s second gold layer on the at least one second under bump metallurgy structure; and bringing the inhibition layer into contact with the second gold layer at a predetermined temperature to form a resultant intermetallic structure between the first substrate and the second substrate thereby bonding the first substrate to the second substrate and forming the bonded structure.