Abstract: Disclosed is a wireless positioning system and method that can perform a high-precision position tracking. The wireless positioning system includes a target device that is an object of wireless positioning, beacon devices and a processing unit. The beacon devices transmits wireless signals and sense reception time points of the wireless signals transmitted from the other beacon devices and the target device and received at time points after the transmission of the wireless signal. The target device receives the wireless signal transmitted from at least one of the beacon devices, and then transmits the wireless signal to the beacon devices. The processing unit obtains the position of the target device by calculating distances between the beacon devices and the target device using information about the reception time points of the wireless signals sensed by the respective beacon devices.

Abstract: The present invention provides an LCD module, in which elements having high resistance to static electricity impact are used as circuit elements of a Printed Circuit Board (PCB) inside a Taped Carrier Package (TCP Board) connecting a front LCD panel to a rear main board, and static electricity introduced via the front LCD panel is dropped to a voltage that the main board can withstand when the static electricity is delivered to the main board, thereby having resistance to high voltage static electricity without requiring the formation or addition of a separate static electricity discharge path.

Abstract: A thin film transistor array substrate for a liquid crystal display includes an insulating substrate with a display area and a peripheral area surrounding the display area. The peripheral area has an upper region above the display area and a lower region below the display area. Signal lines are formed on the substrate such that the signal lines are bundled into a plurality of blocks. Each block has a predetermined number of signal lines. A plurality of first upper repair lines is formed at the upper peripheral region of the substrate, crossing one or more blocks of the signal lines. A plurality of second upper repair lines is formed at the upper peripheral region of the substrate, crossing all of the signal lines. A plurality of first lower repair lines are formed at the lower peripheral region of the substrate, connected to the corresponding first upper repair lines. The first lower repair lines cross the signal lines crossed by the first upper repair lines.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A matrix-type display device having a repair layout, particularly, a matrix-type display device which can be repaired in a pixel unit, is provided. Two or more of signal lines such as scanning signal lines, displaying signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the displaying signal lines and scanning signal lines, the short of the pixel electrode and signal line, and the loss of electrode of a switching element, can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position.

Abstract: A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode.

Abstract: In a method of manufacturing a liquid crystal display using a divisional exposure for a substrate, an overlapping area at the boundary between adjacent shots is provided and the shots left and right to the boundary are exposed in a way that the areas of the shots gradually decreases and gradually increases, respectively, to reduce the brightness difference due to stitch errors between the two shots. For example, the number of unit stitch areas assigned to the left gradually decreases and the number of unit stitch areas assigned to the right shot gradually increases as it goes to the right along the transverse direction in the stitch area. A unit stitch includes an area obtained by dividing a pixel into at least two parts.

Abstract: A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode.

Abstract: Disclosed is a liquid crystal display (LCD). An LCD panel is divided into upper and lower panels, and a scanning direction of gate lines of the upper panel is opposite to that of gate lines of the lower panel. The upper panel includes an upper gate line block having a first gate line formed in the horizontal direction and transmits scanning signals, and upper data lines that cross the first gate line and transmit image signals. And the lower panel includes a lower gate line block having a second gate line, and lower data lines that cross the second gate line and are separated from the upper data lines. Upper and lower gate drivers that provide scanning signals to the gate lines of the upper and lower gate line blocks are located on the sides of the upper and lower panels, respectively. The upper and lower gate drivers supply the scanning signals to the gate lines in sequentially opposite directions.

Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate; a plurality of storage conductors formed on the substrate, each storage conductor including a plurality of branches; a gate insulating layer formed on the gate line and the storage conductor; a semiconductor layer formed on the gate insulating layer; a data conductor formed on the semiconductor layer; a passivation layer formed on the data conductor; and a pixel electrode formed on the passivation layer, wherein at most one of the branches of each storage conductor has an isolated end.

Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position.

Abstract: The present invention relates to a method of forming a pattern on a substrate and a method of manufacturing a liquid crystal display panel using the same. In order to decrease stitch defect, the shot boundary lines for respective layers of patterns do not overlap each other to be dispersed. Specifically, according to a method of forming patterns of the present invention, after a first material layer is first formed on a substrate, a first pattern is formed by performing a first photo etching including divisional light exposure with at least two areas across at least one shot boundary line on the first material layer. Subsequently, after a second material layer is formed on the first pattern, a second pattern is formed by performing a second photo etching including divisional light exposure with at least two areas across at least one shot boundary line on the second material layer. The shot boundary line in the second photo etching is spaced apart from the shot boundary line in the first photo etching.

Abstract: Disclosed is a wireless positioning system and method that can perform a high-precision position tracking. The wireless positioning system includes a target device that is an object of wireless positioning, beacon devices and a processing unit. The beacon devices transmits wireless signals and sense reception time points of the wireless signals transmitted from the other beacon devices and the target device and received at time points after the transmission of the wireless signal. The target device receives the wireless signal transmitted from at least one of the beacon devices, and then transmits the wireless signal to the beacon devices. The processing unit obtains the position of the target device by calculating distances between the beacon devices and the target device using information about the reception time points of the wireless signals sensed by the respective beacon devices.

Abstract: A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area.