Patents by Inventor Yi Liu

Yi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240076496
    Abstract: The present invention provides a thermally conductive silicone composition comprising: (A) at least one alkenyl group-containing organopolysiloxane; (B) at least one organohydrogenpolysiloxane having at least two hydrogen atoms directly bonded to a silicon atom in the molecule; (C1) one or more silane surface-treated alumina particles having a D50 particle size of at least 0.01 ?m but no greater than 5 ?m; (C2) one or more silane surface-treated alumina particles having a D50 particle size of greater than 5 ?m; (D) at least one silane coupling agent; and (E) at least one platinum-based curing catalyst; wherein component (C1) is present in an amount of less than 62% by weight based on the weight of the composition and the component (C2) is present in an amount of less than 80% by weight based on the weight of the composition, which features favorable combination of properties including good flowability, as well as high thermal conductivity and good lap shear strength when cured.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Wentao Xing, Yi Liu, Xiaolong Hu
  • Publication number: 20240078092
    Abstract: A method of assisting a user with the discovery of program features is provided. The method includes detecting a selection of a data structure within a user interface, determining a contextual parameter based on the selected data structure, the contextual parameter associated with a modifiable feature of the selected data structure, determining options for generating program code configured to modify the modifiable feature are available based on the contextual parameter and a predefined inferential relationship between the contextual parameter and the modifiable feature of the selected data structure, and prompting the user in the user interface with information indicating that the determined options for generating the program code are accessible in the user interface.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 7, 2024
    Inventors: Yi LIU, Kristen OSHIRO, David Boyd LUDWIG, IV, Alexander DROTAR, Niraj YADAV, Yu HU, Haiyuan CAO, Haoran WEI, Jeremiah A. NYMAN
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11923237
    Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 11923734
    Abstract: A counter-rotating motor and a high speed blender is described. The counter-rotating motor includes a stator, an inverter, an inner rotor and an outer rotor, the stator is provided with an outer winding and an inner winding, and the outer winding and the inner winding have opposite phase sequences, the inverter is connected in parallel with the outer winding and the inner winding to synchronously supply excitation current to the outer winding and the inner winding, the inner rotor is provided in the inner winding and is used for rotating in a first direction under the effect of the inner winding, and the outer rotor is provided in the outer winding and is used for rotating in a second direction opposite to the first direction under the effect of the outer winding.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: March 5, 2024
    Assignees: GUANGDONG MIDEA WHITE HOME APPLIANCE TECHNOLOGY INNOVATION CENTER CO., LTD., MIDEA GROUP CO., LTD.
    Inventors: Yi Liu, Jianxing Zhao, Fei Wang
  • Patent number: 11920036
    Abstract: A rubber resin material with high dielectric constant and a metal substrate with high dielectric constant are provided. The rubber resin material with high dielectric constant includes a rubber resin composition with high dielectric constant and inorganic fillers. The rubber resin composition with high dielectric constant includes: 40 wt % to 70 wt % of a liquid rubber, 10 wt % to 30 wt % of a polyphenylene ether resin, and 20 wt % to 40 wt % of a crosslinker. A molecular weight of the liquid rubber ranges from 800 g/mol to 6000 g/mol. A dielectric constant of the rubber resin material with high dielectric constant is higher than or equal to 2.0.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 5, 2024
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Hung-Yi Chang, Chien-Kai Wei, Chia-Lin Liu
  • Patent number: 11922027
    Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: March 5, 2024
    Assignee: INNODISK CORPORATION
    Inventors: Chung-Ting Huang, Chung-Yi Lai, Ting-Chiang Liu
  • Patent number: 11918342
    Abstract: Ingestible devices are disclosed that provide very high localization accuracy for the devices when present in the GI tract of a body. Related systems and methods are also disclosed.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: March 5, 2024
    Assignee: Biora Therapeutics, Inc.
    Inventors: Mitchell Lawrence Jones, Yi Liu, Kate LeeAnn Bechtel, Christopher Loren Wahl
  • Patent number: 11920983
    Abstract: Embodiments are directed to an optical spectrometry method, comprising: generating a sequence of 2D Hadamard masks along the time dimension, wherein each 2D Hadamard mask is arranged with a wavelength dimension and a coefficient dimension; detecting an optical signal from light transmitted through the sequence of 2D Hadamard masks; and reconstructing a spectrum to be detected by analyzing the optical signal, wherein each 2D Hadamard mask in the sequence of 2D Hadamard masks comprises a plurality of columns along the wavelength dimension, each column corresponding to a different Hadamard coefficient, and having different respective sequency values along the time dimension.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 5, 2024
    Assignee: XIAMEN UNIVERSITY
    Inventors: Quan Liu, Yi Zhang
  • Patent number: 11921963
    Abstract: A touch structure, a touch display substrate, and a touch display device. The touch structure includes a touch region and a peripheral region surrounding the touch region, wherein the touch region includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other. The touch structure further includes a first touch electrode and a second touch electrode, which are mutually crossed with and insulated from each other, and located in the touch region. The touch structure further includes a first touch trace and a second touch trace, located in the peripheral region. The first touch trace is electrically connected with the first touch electrode at the first edge and the second edge, respectively; the second touch trace is electrically connected with the second touch electrode at the third edge and the fourth edge, respectively.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: March 5, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ping Wen, Shun Zhang, Yi Zhang, Tingliang Liu
  • Patent number: 11919247
    Abstract: A powder-based three-dimensional printing (3DP) method, device and system, and a computer-readable storage medium. The method includes: analyzing printing images of layers corresponding to a part to be printed to determine a target print image and adding a preset mark to the target print image which includes a print image of a target layer that causes a previous powder layer of the target layer to displace during printing; acquiring an image to be printed of a current layer to be printed; identifying the image to be printed to determine whether the preset mark exists on the image to be printed; and if yes, processing the current layer to be printed and/or a previous powder layer of the current layer to be printed such that the previous powder layer of the current layer does not move with powder spreading of the current layer.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: March 5, 2024
    Assignee: KOCEL INTELLIGENT MACHINERY LIMITED
    Inventors: Fan Peng, Donge Zheng, Yinxue Du, Yi Liu, Jun Yang, Cheng Hu, Zixiang Zhou
  • Patent number: 11923349
    Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 11922838
    Abstract: A display panel, comprising a first insulating structural layer, a first crack detection line, a second insulating structural layer and a second crack detection line which are sequentially arranged on a substrate, wherein the first crack detection line and the second crack detection line are both located in a peripheral area and are arranged around a display area, one end of the first crack detection line is configured to receive a detection signal, and the other end of the first crack detection line is configured to output a first output signal, and one end of the second crack detection line is configured to receive a detection signal and the other end of the second crack detection line is configured to output a second output signal.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: March 5, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yu Wang, Yi Zhang, Tingliang Liu, Chang Luo, Hao Zhang, Huijuan Yang, Tinghua Shang, Yang Zhou, Pengfei Yu, Shun Zhang, Xiaofeng Jiang, Huijun Li, Linhong Han
  • Patent number: 11922205
    Abstract: A virtual machine management method and apparatus, a device, and a readable storage medium. The virtual machine management method is applied to a private cloud, and comprises: acquiring a SELinux label, the SELinux label comprising five elements: User, Role, Type, Sensitivity, and Category (S101); setting elements other than Category in the SELinux label as default values (S102); assigning different values to Category according to a preset Category variable combination so as to obtain multiple non-duplicate label groups (S103); and configuring each label group to a virtual machine in the private cloud, so that virtual machines configured with the same label group communicate with each other, and virtual machines configured with different label groups are isolated from each other (S104).
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 5, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Kai Liu, Zheng Xu, Yi Fan, Lihua Yan, Wen Huo
  • Publication number: 20240071854
    Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chien-Li KUO, Kuo-Chio LIU
  • Publication number: 20240074216
    Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Yi Fang Lee, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Karthik Sarpatwari, Scott E. Sills, Sameer Chhajed
  • Publication number: 20240071626
    Abstract: Embodiments of the present disclosure relate to automated validation of medical data. Some embodiments of the present disclosure provide a method for medical data validation. The method comprises obtaining target medical data generated in a medical test and obtaining a machine learning model for validating medical data. The machine learning model represents an association between the medical data and validation results, the validation results indicating information about predetermined actions to be performed on the medical data. The method further comprises determining a target validation result for the target medical data by applying the target medical data to the machine learning model, the target validation result indicating information about a target action selected from the predetermined actions to be performed on the target medical data. Through the solution, it is possible to achieve automated medical data validation with high accuracy and efficiency as well as reduced manual efforts.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicants: Roche Diagnostics Operations, Inc., Qilu Hospital of Shandong University
    Inventors: Daquan Liu, Yin Qian, Xiaojun Tao, Hongchun Wang, Weibin Xing, Chenxi Zhang, Yi Zhang, Qi Zhou
  • Publication number: 20240071803
    Abstract: Methods and systems for dry etching are disclosed. The system includes a wafer clamp ring having a central opening through which a substrate may be treated and a plurality of smaller, outer support holes for receiving pins from plunger assemblies. The outer support holes are tapered and change in diameter. The tapered shape reduces horizontal shifting of the wafer clamp ring which can occur as the wafer clamp ring is moved up-and-down during operational use. The reduced shifting increases wafer yield along the edges of the wafer.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Fu-Yi Liu, Chou-Feng Lee, Chih-Hsien Hsu
  • Publication number: 20240074328
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240069098
    Abstract: Disclosed are a fault diagnosis circuit, method and apparatus, and computer readable storage medium. The fault diagnosis circuit includes a safety protection circuit electrically connected to a protected circuit and a diagnosis module electrically connected to the safety protection circuit. The safety protection circuit is configured to perform check operation on stored data in the protected circuit to obtain first check data, perform error injection on second check data corresponding to the stored data, and generate a first check result signal based on the first check data and the second check data after the error injection. The diagnosis module is configured to diagnose faults in the safety protection circuit based on the first check result signal. From embodiments of this disclosure, the safety protection circuit is diagnosed faults through a simple hardware structure, to eliminate the faults based on a diagnosis result, thereby ensuring normal operation of a chip.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 29, 2024
    Applicant: Horizon (Shanghai) Artificial Intelligence Technology Co., Ltd.
    Inventors: Zheng WU, Wenxing LI, Yi ZHOU, Jing LI, Qingyu LIU