Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

Abstract: Embodiments relate to reusable absorbent inserts, assemblies, and methods for use, the inserts including a configurable pad and pad collection sleeve. The configurable pad includes a first section and a second section, the second section separated from the first section at least partially by a folding guide. The configurable pad has an unfolded pad plan surface area comprising an unfolded pad width when the reusable absorbent insert is in an unfolded, flat-out configuration. The pad collection sleeve has an unfolded sleeve plan surface area including an unfolded sleeve width when the reusable absorbent insert is in an unfolded, flat-out configuration. The unfolded pad width is greater than or substantially equal to the unfolded sleeve width.

Abstract: In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.

Abstract: A multiple sensor-fusing based interactive training system, including a posture sensor, a sensing module, a computing module, and a display module, is provided. The posture sensor is configured to sense posture data and myoelectric data related to a training action. The sensing module is configured to output limb torque data according to the posture data, and output muscle group activation time data according to the myoelectric data. The computing module is configured to respectively convert the limb torque data and the muscle group activation time data into a moment-skeleton coordinate system and a muscle strength eigenvalue-skeleton coordinate system according to a skeleton coordinate system, perform fusion calculation, calculate evaluation data based on a result of the fusion calculation, and judge that the training action corresponds to a known exercise action according to the evaluation data. The display module is configured to display the evaluation data and the known exercise action.

Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dielectric layer over the substrate, the first fin structure, and the second fin structure. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

Abstract: A system for measuring impedance which is tolerant of connection errors includes a measuring instrument and a relay plate. The relay plate includes a plurality of relay groups. A relay group comprises a first channel, a second channel, a third channel, and a fourth channel. The first to fourth channels are electrically connected to a conductive pin of the product. The relay board further comprises a first voltage interface, a second voltage interface, a first current interface, and a second current interface, the first voltage interface is electrically connected to the first channel, the first current interface is electrically connected to the second channel, the second voltage interface is electrically connected to the third channel, and the second current interface is electrically connected to the fourth channel, a control unit being able to switch between these when connected to obtain impedance measurements.

Abstract: A method includes receiving a service request from a vehicle within a geographic area, receiving a first set of data from the vehicle comprising a position of the vehicle within the geographic area, a direction that the vehicle is facing, and a field of view for an augmented reality display associated with the vehicle, obtaining historical traffic data associated with the geographic area, identifying one or more traffic infrastructures within the field of view of the augmented reality display based on a map associated with the geographic area, the historical traffic data, the position of the vehicle, and the direction the vehicle is facing, generating an augmented reality image for the one or more traffic infrastructures based on the historical traffic data and the field of view of the augmented reality display, and sending the augmented reality image to the vehicle.

Abstract: The present application discloses a method for fabricating a semiconductor device with a self-aligned landing pad. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer. The landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

Abstract: A coupled physiological signal measurement method, a coupled physiological signal measurement system and a graphic user interface are provided. The coupled physiological signal measurement method includes the following steps. An original myoelectric signal is captured. A capacitance value of a skin is obtained. The original myoelectric signal is compensated according to the capacitance value of the skin. The step of compensating the original myoelectric signal according to the capacitance value includes the following steps. The original myoelectric signal is decomposed to obtain several myoelectric sub-signals corresponding to several frequencies, wherein each myoelectric sub-signal has an amplitude variation. The amplitude variations of the myoelectric sub-signals are respectively adjusted according to the capacitance value of the skin. The adjusted myoelectric sub-signals are merged to obtain a compensated myoelectric signal.

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: The present disclosure provide a method of preparing semiconductor device involving planarization processes. The method includes introducing dopants into the exposed portions of the substrate to form doped portions of the substrate; forming a crystalline overlayer on the doped portions of the substrate, wherein the crystalline overlayer has a conductivity lower than that of the doped portions of the substrate. The crystalline overlayer is formed by an epitaxial growth process, the crystalline overlayer is formed as a saddle shape, and the crystalline overlayer has an excess portion protruding from the substrate.