Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A finFET device and methods of forming a finFET device are provided. The device includes a fin and a capping layer over the fin. The device also includes a gate stack over the fin, the gate stack including a gate electrode and a gate dielectric. The gate dielectric extends along sidewalls of the capping layer. The device further includes a gate spacer adjacent to sidewalls of the gate electrode, the capping layer being interposed between the gate spacer and the fin.

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.

Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

Abstract: A double-sided flexible circuit board includes a flexible substrate, a first circuit layer, a second circuit layer, an insulating protection layer and a plurality of through circuit lines. The first and second circuit layers are located on a top surface and a bottom surface of the flexible substrate, respectively. The insulating protection layer covers a supporting line of the second circuit layer such that the supporting line is located between the flexible substrate and the insulating protection layer. The insulating protection layer can provide electrical insulation to the supporting line of the second circuit layer to avoid short circuit conditions of the double-sided flexible circuit board during test.

Abstract: A method includes receiving a request from a vehicle to perform a computing task, selecting a machine learning model from among a plurality of machine learning models based at least in part on the request, and predicting an amount of computing resources needed to perform the computing task using the selected machine learning model.

Abstract: The present disclosure relates a lithographic substrate marking tool. The tool includes a first electromagnetic radiation source disposed within a housing and configured to generate a first type of electromagnetic radiation. A radiation guide is configured to provide the first type of electromagnetic radiation to a photosensitive material over a substrate. A second electromagnetic radiation source is disposed within the housing and is configured to generate a second type of electromagnetic radiation that is provided to the photosensitive material.

Abstract: A system for measuring impedance which is tolerant of connection errors includes a measuring instrument and a relay plate. The relay plate includes a plurality of relay groups. A relay group comprises a first channel, a second channel, a third channel, and a fourth channel. The first to fourth channels are electrically connected to a conductive pin of the product. The relay board further comprises a first voltage interface, a second voltage interface, a first current interface, and a second current interface, the first voltage interface is electrically connected to the first channel, the first current interface is electrically connected to the second channel, the second voltage interface is electrically connected to the third channel, and the second current interface is electrically connected to the fourth channel, a control unit being able to switch between these when connected to obtain impedance measurements.

Abstract: The present application relates to a sizing agent composition, a carbon fiber material and a composite material. The sizing agent composition comprises specific compositions, thereby producing a sizing agent having emulsion droplets with specific diameter. The sizing agent has excellent emulsion stability, and it can efficiently improve hygroscopicity and dimensional stability of the carbon fiber material. Besides, the sizing agent can improve bonding properties between the carbon fiber material and resin matrix, therefore enhancing properties of the composite material.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a positions of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

Abstract: A semiconductor structure having doped wells and a method of forming is provided. The doped wells may utilize parallel implantation techniques and tilt implantation techniques to form wells having less lateral diffusion and less vertical doping.

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.