Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A feature extraction process is performed to obtain features based on the LDR images and the HDR images. A second neural network for video stabilization is trained according to the LDR images and the HDR images based on a loss function by minimizing a loss value of the loss function to generate stabilized HDR images in a time-dependent manner, where the loss value of the loss function depends upon the features. An HDR classifier is constructed according to the LDR images and the HDR images. The stabilized HDR images are classified by using the HDR classifier to generate a reward value, where the loss value of the loss function further depends upon the reward value.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: The present disclosure provides an anti-fogging material and a manufacturing method thereof. The anti-fogging material includes a crosslinked polymer obtained by curing an anti-fogging composition, wherein the anti-fogging composition includes an ionic compound, a hard compound with two or more acrylate functional groups at the terminus thereof, and a surface active compound.

Abstract: A polymer includes a repeating unit M and a repeating unit D, the repeating unit M is —COC6H6CONHCH2CH2O—, the repeating unit D is —COC6H6COOCH2CH2O—, and a molar ratio of the repeating unit M to the repeating unit D is 1:6 to 1:999.

Abstract: A copolymer includes a repeating unit corresponding to polyether sulfone and a repeating unit corresponding to vinyl monomer. The repeating unit corresponding to polyether sulfone has a repeating number of 200 to 450, and the repeating unit corresponding to vinyl monomer has a repeating number of 20 to 100. The copolymer can be blended with another polymer such as polyphenylene sulfide to form a blend.

Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

Abstract: A method for adjusting a workpiece-supporting module includes: setting initial support position information of a workpiece, the initial support position information including positions of support devices and a spacing value for separating the support devices; according to the initial support position information, applying a finite element method to analyze a CAD file of the workpiece to obtain workpiece deformation information; according to the workpiece deformation information and target workpiece deformation information, realizing support position information corresponding to each support device, the support position information including X-axis coordinates and Y-axis coordinates; according to the support position information and a conversion program, obtaining a Z-axis coordinate and a normal vector of each support devices; and, according to the support position information, the Z-axis coordinate and the normal vector, adjusting the position and the angle of each support device.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: A method for training a patterning process model, the patterning process model configured to predict a pattern that will be formed by a patterning process. The method involves obtaining an image data associated with a desired pattern, a measured pattern of the substrate, a first model including a first set of parameters, and a machine learning model including a second set of parameters; and iteratively determining values of the first set of parameters and the second set of parameters to train the patterning process model. An iteration involves executing, using the image data, the first model and the machine learning model to cooperatively predict a printed pattern of the substrate; and modifying the values of the first set of parameters and the second set of parameters such that a difference between the measured pattern and the predicted pattern is reduced.

Abstract: The present invention provides a method for manufacturing a neural probe incorporated with an optical waveguide. The method for manufacturing a neural probe incorporated with an optical waveguide comprises the following steps. A mold-filling step, for providing a base with at least one groove formed therein. A disposing step, for disposing and overlaying a substrate having a plurality of electrode parts on the groove of the base. A combining step, for solidifying the photosensitive adhesive by a solidification process, the solidified photosensitive adhesive forming an optical waveguide and being combined with the substrate. A mold-releasing step, for removing the base from the optical waveguide and the substrate, the substrate and the optical waveguide forming a product.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first conductive layer positioned above the substrate, a bottom conductive layer positioned above the first conductive layer and electrically coupled to the first conductive layer, a programmable insulating layer positioned on the bottom conductive layer, a top conductive layer positioned on the programmable insulating layer, and a redistribution structure positioned above the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: Provided are anti-CD73 antibodies, variants, and antigen binding fragments thereof. The antibodies, the variants, and the antigen binding fragments thereof bind to human CD73 with high affinity, and suppress the enzymatic activity of CD73, and optionally induce CD73 internalization. Further provided are isolated nucleic acid molecules encoding the anti-CD73 antibodies, the variants, and the antigen binding fragments thereof, and a related expression vector and a host cell. Provided is a method for preparing the anti-CD73 antibodies, the variants, and the antigen binding fragments thereof. Further provided are related pharmaceutical compositions and a method for using said pharmaceutical compositions in treating a subject.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Abstract: System, methods, and other embodiments described herein relate to improving execution of processing requests by an edge server. In one embodiment, a method includes predicting a number of computing requests from vehicles for execution by the edge server using a prediction solver for a time period that is forthcoming. The prediction solver may predict the number of computing requests using a prediction model selected in association with service constraints of the edge server and information from an additional server. The method also includes determining a request handling scheme using an optimization solver according to the number of computing requests, the service constraints of the edge server, and a service area of the edge server. The method also includes communicating the request handling scheme and a resource schedule to the edge server on a condition that a resources criteria are satisfied for the time period.

Abstract: The present application discloses a method for fabricating a semiconductor device with an oxidized intervention layer. The method includes providing a substrate; forming a tunneling insulating layer over the substrate; forming a floating gate over the tunnel oxide layer; forming a dielectric layer over the floating gate; forming a control gate over the dielectric layer; and performing a lateral oxidation process over the substrate, wherein a process temperature of the lateral oxidation process is between about 300° C. and about 600° C.

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.