Abstract: A copolymer includes a repeating unit corresponding to polyether sulfone and a repeating unit corresponding to vinyl monomer. The repeating unit corresponding to polyether sulfone has a repeating number of 200 to 450, and the repeating unit corresponding to vinyl monomer has a repeating number of 20 to 100. The copolymer can be blended with another polymer such as polyphenylene sulfide to form a blend.

Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

Abstract: A method for adjusting a workpiece-supporting module includes: setting initial support position information of a workpiece, the initial support position information including positions of support devices and a spacing value for separating the support devices; according to the initial support position information, applying a finite element method to analyze a CAD file of the workpiece to obtain workpiece deformation information; according to the workpiece deformation information and target workpiece deformation information, realizing support position information corresponding to each support device, the support position information including X-axis coordinates and Y-axis coordinates; according to the support position information and a conversion program, obtaining a Z-axis coordinate and a normal vector of each support devices; and, according to the support position information, the Z-axis coordinate and the normal vector, adjusting the position and the angle of each support device.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: A method for training a patterning process model, the patterning process model configured to predict a pattern that will be formed by a patterning process. The method involves obtaining an image data associated with a desired pattern, a measured pattern of the substrate, a first model including a first set of parameters, and a machine learning model including a second set of parameters; and iteratively determining values of the first set of parameters and the second set of parameters to train the patterning process model. An iteration involves executing, using the image data, the first model and the machine learning model to cooperatively predict a printed pattern of the substrate; and modifying the values of the first set of parameters and the second set of parameters such that a difference between the measured pattern and the predicted pattern is reduced.

Abstract: The present invention provides a method for manufacturing a neural probe incorporated with an optical waveguide. The method for manufacturing a neural probe incorporated with an optical waveguide comprises the following steps. A mold-filling step, for providing a base with at least one groove formed therein. A disposing step, for disposing and overlaying a substrate having a plurality of electrode parts on the groove of the base. A combining step, for solidifying the photosensitive adhesive by a solidification process, the solidified photosensitive adhesive forming an optical waveguide and being combined with the substrate. A mold-releasing step, for removing the base from the optical waveguide and the substrate, the substrate and the optical waveguide forming a product.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first conductive layer positioned above the substrate, a bottom conductive layer positioned above the first conductive layer and electrically coupled to the first conductive layer, a programmable insulating layer positioned on the bottom conductive layer, a top conductive layer positioned on the programmable insulating layer, and a redistribution structure positioned above the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: Provided are anti-CD73 antibodies, variants, and antigen binding fragments thereof. The antibodies, the variants, and the antigen binding fragments thereof bind to human CD73 with high affinity, and suppress the enzymatic activity of CD73, and optionally induce CD73 internalization. Further provided are isolated nucleic acid molecules encoding the anti-CD73 antibodies, the variants, and the antigen binding fragments thereof, and a related expression vector and a host cell. Provided is a method for preparing the anti-CD73 antibodies, the variants, and the antigen binding fragments thereof. Further provided are related pharmaceutical compositions and a method for using said pharmaceutical compositions in treating a subject.

Abstract: System, methods, and other embodiments described herein relate to improving execution of processing requests by an edge server. In one embodiment, a method includes predicting a number of computing requests from vehicles for execution by the edge server using a prediction solver for a time period that is forthcoming. The prediction solver may predict the number of computing requests using a prediction model selected in association with service constraints of the edge server and information from an additional server. The method also includes determining a request handling scheme using an optimization solver according to the number of computing requests, the service constraints of the edge server, and a service area of the edge server. The method also includes communicating the request handling scheme and a resource schedule to the edge server on a condition that a resources criteria are satisfied for the time period.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Abstract: The present application discloses a method for fabricating a semiconductor device with an oxidized intervention layer. The method includes providing a substrate; forming a tunneling insulating layer over the substrate; forming a floating gate over the tunnel oxide layer; forming a dielectric layer over the floating gate; forming a control gate over the dielectric layer; and performing a lateral oxidation process over the substrate, wherein a process temperature of the lateral oxidation process is between about 300° C. and about 600° C.

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: The disclosure provides an active peptide with an anti-lipid oxidation function and a preparation method and application thereof and belongs to the technical field of plant-derived biologically active peptides. In the disclosure, oil processing by-products, namely oil crops after oil extraction, are used as the raw materials, and the raw materials are subjected to the steps of protein extraction, infrared pretreatment, proteolysis, freeze-drying, lipophilic part extraction, vacuum concentration and drying to prepare an anti-lipid oxidation peptide having the functional characteristics of scavenging DPPH free radicals, chelating metal ions, inhibiting lipid peroxidation, prolonging vegetable oil oxidation induction time, improving emulsion stability and the like.

Abstract: An optical sensor includes pixels disposed in a substrate. A light collimating layer is disposed on the substrate and includes a transparent layer, a light-shielding layer, and transparent pillars. The transparent layer blanketly disposed on the substrate covers the pixels and the region between the pixels. The light-shielding layer is disposed on the transparent layer and between the transparent pillars. The transparent pillars penetrating through the light-shielding layer are correspondingly disposed on the pixels.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.