Patents by Inventor Yin Liu

Yin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220069831
    Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.
    Type: Application
    Filed: May 28, 2021
    Publication date: March 3, 2022
    Inventors: SHIH-HSIUNG HUANG, YING-CHENG WU, CHIEN-MING WU, KAI-YIN LIU
  • Patent number: 11264109
    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih
  • Publication number: 20220003419
    Abstract: A cooking gas safety apparatus is shown and described. The apparatus includes a cooking gas safety valve assembly that supplies cooking gas to one or more burners. The cooking gas safety assembly includes at least one coil that is energizable to hold the valve assembly in an open position when subjected to a current that exceeds a threshold value and a hold open circuit. The hold open circuit comprises the coil and a hot surface igniter that is in electrical communication with the coil. The valve assembly is actuated by manually opening the valve and energizing the igniter such that it receives a threshold current that corresponds to an autoignition temperature of the gas. At the threshold current, an electromagnet in the cooking gas safety valve assembly holds the valve open so that it remains open without user intervention. In the event of an igniter failure, the current flow to the coil ceases, causing the valve to shut and cease gas flow to the burner.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 6, 2022
    Inventors: Brian C. Dougherty, Erik Bothe, Jack A. Shindle, Yin Liu
  • Publication number: 20210391568
    Abstract: The disclosure discloses a method for preparing a high-voltage cathode material by body modification and regeneration of a waste lithium cobaltate material.
    Type: Application
    Filed: April 16, 2021
    Publication date: December 16, 2021
    Inventors: Yingjie Zhang, Peng Dong, Qi Meng, Siyuan Zhou, Qingxiang Li, Shaoqiang Zhou, Jianguo Duan, Xue Li, Yin Liu, Duanyun Chen
  • Publication number: 20210382512
    Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.
    Type: Application
    Filed: August 18, 2021
    Publication date: December 9, 2021
    Inventors: CHE-WEI CHANG, KAI-YIN LIU, LIANG-HUAN LEI, SHIH-HSIUNG HUANG
  • Publication number: 20210375780
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Xin-Hua Huang, Ping-Yin Liu
  • Patent number: 11189515
    Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hung Wang, Ping-Yin Liu, Yeong-Jyh Lin, Yeur-Luen Tu
  • Patent number: 11182596
    Abstract: A computer-implemented method comprising: monitoring, by a computing device, live sensor data received from one or more sensor devices; detecting, by the computing device, abnormal behavior of one or more individuals or objects based on the monitoring the live sensor data; determining, by the computing device, a deficiency of a facility based on the detecting the abnormal behavior; and executing, by the computing device, a computer-based instruction based on the deficiency of the facility.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wen Wang, Yan Bin Fu, Yi Wu, Qing Jun Gao, Shuang Yin Liu, Raymond Lee Man Kong
  • Publication number: 20210335646
    Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Chang-Chen Tsao
  • Publication number: 20210332448
    Abstract: In certain aspects, the disclosure relates to methods of quantifying integration of a recombinant vector nucleic acid into a target cell's genome. The present disclosure also provides compositions and kits, including particular primers and probes, for performing the quantitation.
    Type: Application
    Filed: March 8, 2021
    Publication date: October 28, 2021
    Inventors: Rajitha Doddareddy, Hsing-Yin Liu, Levi Gray-Rupp, Tong-Yuan Yang
  • Patent number: 11158866
    Abstract: A microbial fuel cell and a method of manufacturing the same are provided. The microbial fuel cell includes a cathode, an anode, and a microbial community. The anode is made of an activated carbon prepared from waste coffee ground as an electrode material, and the microbial community is adhered to the surface of the activated carbon. Since the activated carbon prepared from waste coffee ground is beneficial for the adhesion of various microbial communities to form a biofilm, the electron transfer efficiency of the microbial fuel cell may be improved.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 26, 2021
    Assignee: National Tsing Hua University
    Inventors: Yu-Hsuan Hung, Han-Yi Chen, Tzu-Yin Liu
  • Publication number: 20210312614
    Abstract: A medical image recognition method includes the following steps: establishing an image recognition model, wherein the image recognition model is generated by inputting a plurality of labeled medical image slices in a plurality of initial medical image piles into a neural network; and in response to determining that the accuracy of the image recognition model is not higher than an accuracy threshold; calculating a plurality of image change rates corresponding to each of a plurality of initial medical image slices or the initial medical image piles formed by the initial medical image slices according to the image recognition model; selecting at least one of the initial medical image piles or the initial medical image slices as a training medical image slice according to the image change rates; obtaining the target range of each training medical image slice to re-establish the image recognition model.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 7, 2021
    Inventor: Ting Yin LIU
  • Publication number: 20210312960
    Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
  • Publication number: 20210305292
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Patent number: 11128280
    Abstract: A filter can perform two filtering processes. The filter includes a switching circuit, a first filter circuit, and a second filter circuit. The first filter circuit is coupled to the switching circuit. The second filter circuit is coupled to the switching circuit. The first filter circuit performs a first filtering process on an input signal according to a state of the switching circuit. The first filter circuit and the second filter circuit work together to perform a second filtering process on the input signal according to the state of the switching circuit.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 21, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yun-Tse Chen, Kai-Yin Liu
  • Patent number: 11127725
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Yin Liu, Yeong-Jyh Lin, Chi-Ming Chen
  • Publication number: 20210273167
    Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
  • Publication number: 20210272928
    Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 2, 2021
    Inventors: Xin-Hua Huang, Kuan-Liang Liu, Kuo Liang Lu, Ping-Yin Liu
  • Patent number: 11094575
    Abstract: In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Chang-Chen Tsao
  • Patent number: 11086374
    Abstract: A transmission interface circuit includes a power supply port, a first power path, first data transmission path, second power path and controller. The first power port is coupled to the storage device to provide the storage device with power. The first data transmission path is coupled between the storage device and the electronic device to perform data transmission between the storage device and the electronic device. The second power port is coupled to the electronic device to provide the electronic device with power. The controller respectively control enables or disables the first power path, the second power path and the first data transmission path according to the information transmitted from the electronic device.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 10, 2021
    Assignee: JMicron Technology Corp.
    Inventors: Chao-Yin Liu, Cheng-Ping Fang