Patents by Inventor Ying Hao

Ying Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PATTERN FORMATION METHOD AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210193480
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Yi-Chang LEE, Jiann-Horng LIN, Chih-Hao CHEN, Ying-Hao WU, Wen-Yen CHEN, Shih-Hua TSENG, Shu-Huei SUEN
  • BENDING SENSING DEVICE
    Publication number: 20210181042
    Abstract: A bending sensing device comprises a substrate, a piezoresistive thin film and at least a pair of electrodes. The substrate is flexible and having a two-dimensional structure, and a material of the substrate is mica. The piezoresistive thin film is disposed on the substrate whose material is inorganic compound comprising zinc oxide (ZnO), doped ZnO, germanium (Ge), doped Ge, or any combinations thereof. The at least a pair of electrodes are disposed separately on two terminals of at least a measurement section of the piezoresistive thin film to electrically connect the measurement section.
    Type: Application
    Filed: July 3, 2020
    Publication date: June 17, 2021
    Inventors: Ying-Hao Chu, Min Yen
  • RESIDUAL TOXICANT DETECTION DEVICE
    Publication number: 20210156791
    Abstract: A residual toxicant detection device for testing residual toxicant in an aqueous solution is disclosed, which includes a first space cavity, a second space cavity, a connecting frame and a sensing cavity. The first space cavity includes a light source and a lens. The second space cavity includes a photo sensor and a circuit module. The connecting frame is configured to connect the first space cavity and the second space cavity. The sensing cavity for receiving an aqueous solution is formed between the first space cavity and the second space cavity and at one side of the connecting frame. The light source emits a light with a wavelength range. The photo sensor receives the sensing signal of the light passing through the sensing cavity. The circuit module is configured to calculate the absorbance and the variation in absorbance of the residual toxicants in the aqueous solution.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 27, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Hao HSU, Jui-Hung TSAI, Ying-Hao WANG, Chia-Jung CHANG
  • Image data retrieving method and image data retrieving device
    Patent number: 11017254
    Abstract: An image data retrieving method and an image data retrieving device are provided. The image data retrieving method includes: receiving an image including a plurality of data from a communication interface; obtaining a plurality of regions of interest from the image, wherein each of the regions of interest is a data image including at least one of the data; dividing the regions of interest into a plurality of groups, wherein at least one of the data included in the regions of interest of each of the groups has a same type; combining the regions of interest of each of the groups into a to-be-recognized image; and performing an optical character recognition to the to-be-recognized image corresponding to each of the groups respectively to obtain the data corresponding to the regions of interest of each of the groups.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 25, 2021
    Assignee: Wistron Corporation
    Inventors: Ying-Hao Peng, Zih-Yang Huang
  • Bonding pad on a back side illuminated image sensor
    Patent number: 11011566
    Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Volume Chien, I-Chih Chen, Hsin-Chi Chen, Hung-Ta Huang, Ying-Hao Chen, Ying-Lang Wang
  • Methods for calibrating correlation between voltage and grayscale value of display panels
    Patent number: 11004386
    Abstract: Method and system for calibrating a plurality of voltages of a light-emitting element and a plurality of grayscale values of a respective pixel of the light-emitting element on a display panel are provided. The method may include determining a mapping correlation between the plurality of voltages of the light-emitting element and a plurality of luminance values of the light-emitting element, determining N grayscale values of the pixel, and determining N first luminance values each corresponding to the respective one of the N grayscale values. The method may also include determining N first voltages mapped to the N first luminance values using the mapping correlation and determining, of each one of the N first luminance values, (M?1) second luminance values. Each one of the (M?1) second luminance values may correspond to a different dimmed luminance value of the respective first luminance value.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 11, 2021
    Assignee: KUNSHAN YUNYINGGU ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Chun-Ta Wu, Yu-Hsing Chuang, Ying-Hao Tu, Wu-Hsiung Cheng
  • Image sensor having stress releasing structure and method of forming same
    Patent number: 10985199
    Abstract: A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen, Chun-Wei Chia
  • Adhesion promoter apparatus and method
    Patent number: 10983278
    Abstract: An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kai-Fang Cheng, Hai-Ching Chen, Tien-I Bao
  • THERMALLY CONDUCTIVE MOLDING COMPOUND STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES
    Publication number: 20210104485
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.
    Type: Application
    Filed: November 25, 2020
    Publication date: April 8, 2021
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Electronic device casing and electronic device
    Patent number: 10965016
    Abstract: An electronic device casing adapted to cover an antenna is provided. The electronic device casing includes a supporting layer and a carbon fiber layer. The carbon fiber layer is disposed on a surface of the supporting layer and includes a signal passing region having a plurality of slits and a plurality of microstructures separated by the slits. The signal passing region is adapted to cover the antenna, and a signal excited by the antenna is adapted to pass through the supporting layer and the slits so as to pass through the electronic device casing. An electronic device having the electronic device casing is further provided.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 30, 2021
    Assignee: HTC Corporation
    Inventors: Ying-Hao Yeh, Sheng-Wen Su
  • OPTICAL BENCH, METHOD OF MAKING AND METHOD OF USING
    Publication number: 20210088737
    Abstract: A method of forming an optical bench includes forming a reflector layer over a sloping side of a substrate. The method includes depositing a redistribution layer over the substrate. The method includes disposing an under bump metallization (UBM) layer over the redistribution layer. The method includes forming a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer. The method includes mounting a first optical component over an uppermost portion of the substrate, wherein the reflector layer is configured to reflect an electromagnetic wave from the first optical component, and the first optical component is mounted outside the trench.
    Type: Application
    Filed: December 9, 2020
    Publication date: March 25, 2021
    Inventors: Ying-Hao KUO, Shang-Yun HOU, Wan-Yu LEE
  • Thermally conductive structure for heat dissipation in semiconductor packages
    Patent number: 10957559
    Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • HEAT DISSIPATION STRUCTURES
    Publication number: 20210082784
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
  • APPARATUS, SYSTEM, AND METHOD OF PROVIDING A CONTENT LEVEL MONITOR
    Publication number: 20210072066
    Abstract: An apparatus, system and method for providing a consumable level monitor for association with a content-filled consumable. The embodiments may include a sensing module suitable to sense the consumable level; and a communications module suitable for receiving the consumable level from the sensing module, and for communicating the consumable level to a user.
    Type: Application
    Filed: May 3, 2019
    Publication date: March 11, 2021
    Applicant: NYPRO INC.
    Inventors: Amanda Williams, Julio Daniel Oropeza, Yu-Chang Lee, Ying Hao Lee, Martin Johnson, Marc Theeuwes, Stefan Vaes, Toon Diels
  • APPARATUS, SYSTEM, AND METHOD OF PROVIDING A SOLIDS LEVEL MONITOR
    Publication number: 20210072067
    Abstract: An apparatus, system and method for providing a consumable level monitor for association with a solid content-filled consumable. The embodiments may include a sensing module embedded in a label associated with the consumable suitable to sense the consumable level; and a visual indicator suitable to receive the consumable level from the sensing module, and for communicating the consumable level to a user.
    Type: Application
    Filed: May 3, 2019
    Publication date: March 11, 2021
    Applicant: NYPRO INC.
    Inventors: Amanda Williams, Julio Daniel Oropeza, Yu-Chang Lee, Ying Hao Lee, Martin Johnson, Marc Theeuwes, Stefan Vaes, Toon Diels
  • Cathode layer and membrane electrode assembly of solid oxide fuel cell
    Patent number: 10944115
    Abstract: A cathode layer and a membrane electrode assembly of a solid oxide fuel cell are provided. The cathode layer consists of a plurality of perovskite crystal films, and the average change rate of linear thermal expansion coefficients of these perovskite crystal films is about 5% to 40% along the thickness direction. The membrane electrode assembly includes the above-mentioned cathode layer, and the linear thermal expansion coefficients of these perovskite crystal films are reduced towards the solid electrolyte layer of the membrane electrode assembly.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 9, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Tzu-Chi Chou, Kuo-Chuang Chiu, Tzu-Yu Liu, Yung-Hsiang Juan, Ying-Hao Chu
  • Pattern formation method and method for manufacturing a semiconductor device
    Patent number: 10943791
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
  • METAL-INSULATOR-METAL CAPACITORS WITH HIGH BREAKDOWN VOLTAGE
    Publication number: 20210057517
    Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting CHEN, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Chuang
  • Method for fabricating heteroepitaxial semiconductor material on a mica sheet
    Patent number: 10930496
    Abstract: A method for fabricating heteroepitaxial semiconductor material on a mica sheet is disclosed. Firstly, a mica substrate is provided. Then, at least one semiconductor film is deposited on the mica substrate to form a flexible substrate whose flexibility is applied to various applications, such as wearable devices, portable photoelectric equipment, or improving the speed and bandwidth of commercial and military systems, such that the flexible substrate has the competitiveness in the market.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 23, 2021
    Assignee: National Chiao Tung University
    Inventors: Yi-Chia Chou, Wan-Jung Lo, Ying-Hao Chu
  • IMAGE SENSOR AND METHOD OF FORMING THE SAME
    Publication number: 20210020671
    Abstract: A back side illumination (BSI) image sensor is provided. The BSI image sensor includes a semiconductor substrate, a first dielectric layer, a reflective element, a second dielectric layer and a color filter layer. The semiconductor substrate has a front side and a back side. The first dielectric layer is disposed on the front side of the semiconductor substrate. The reflective element is disposed on the first dielectric layer, in which the reflective element has an inner sidewall contacting the first dielectric layer, and the inner sidewall has a zigzag profile. The second dielectric layer is disposed on the first dielectric layer and the reflective element. The color filter layer is disposed on the backside of the semiconductor substrate.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN