Abstract: A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.

Abstract: A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.

Abstract: The invention provides 3-carboxypropyl-aminotetralin compounds of formula (I): wherein R1, R2, R3, R4, R5, and R6 are defined in the specification, or a pharmaceutically-acceptable salt thereof, that are antagonists at the mu opioid receptor. The invention also provides pharmaceutical compositions comprising such compounds, methods of using such compounds to treat conditions associated with mu opioid receptor activity, and processes and intermediates useful for preparing such compounds.

Abstract: An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.

Abstract: A multi-reflection structure including a substrate and pyramid is provided. The substrate includes an inversed pyramid shaped recess having at least three first reflection sidewalls. The pyramid is disposed on the substrate and located in the inversed pyramid shaped recess. The pyramid has at least three second reflection sidewalls, wherein the normal of each of the second reflection sidewalls and the normal of each of the first reflection sidewalls are not located in the same plane. Furthermore, a photo-electric device is also provided in the present application.

Abstract: A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage.

Abstract: A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.

Abstract: A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage.

Abstract: Systems and methods for supporting a liquid against a vacuum pressure in a chamber can enable analysis of the liquid surface using vacuum-based chemical analysis instruments. No electrical or fluid connections are required to pass through the chamber walls. The systems can include a reservoir, a pump, and a liquid flow path. The reservoir contains a liquid-phase sample. The pump drives flow of the sample from the reservoir, through the liquid flow path, and back to the reservoir. The flow of the sample is not substantially driven by a differential between pressures inside and outside of the liquid flow path. An aperture in the liquid flow path exposes a stable portion of the liquid-phase sample to the vacuum pressure within the chamber. The radius, or size, of the aperture is less than or equal to a critical value required to support a meniscus of the liquid-phase sample by surface tension.

Abstract: An apparatus is disclosed for aligning socket housing segments for an area array device. Each socket housing segment includes at least a first surface and a second surface, with the second surface opposite the first surface. The second surface of each socket housing segment provides electrical connections for a portion of the area array device. Socket contact pads are disposed on the first surfaces of the plurality of socket housing segments. The socket contact pads correspond to substrate contact pads disposed on a substrate. One or more alignment structures are disposed at a space between the socket housing segments. Each alignment structure is coupled to at least two of the socket housing segments. The one or more alignment structures maintain a predetermined alignment of each socket housing segment so that the socket contact pads align with the substrate contact pads during a surface mount connection process.

Abstract: An antenna device includes a housing having a lower portion for coupling to a non-magnetic option coupler of a vehicle, an insulating member engaged in an upper chamber of the housing, a conductor member engaged into a central bore of the insulating member for engaging with the non-magnetic option coupler, a conductive coupling element having a lower portion engaged into the housing, and a coaxial radiating assembly includes a coaxial radiating device having a central radiating member for connecting to the conductor member, and a peripheral radiating member for connecting to the conductive coupling element, and an insulating element mounted between the central radiating member and the cylindrical radiating member.

Abstract: The invention provides an efficient method for preparing 3-endo-(8-azabicyclo[3.2.1]oct-3-yl)benzamide by hydrogenation, under controlled conditions, of an amino-protected 3-(8-azabicyclo[3.2.1]oct-2-en-3-yl)benzamide intermediate in which the amino-protecting group is removable by catalytic hydrogenation.

Abstract: A patterned substrate for a touch screen sensor assembly that includes a plurality of electrodes that are formed from a first transparent conductive layer that has a first surface resistivity. The substrate also has a plurality of traces that may be used to couple the electrodes controller associated with the touch screen sensor assembly. The traces are formed from a second conductive layer that has a second surface resistivity that is less than the surface resistivity of the first conductive layer. The first and second conductive layers may be formed from indium tin oxide (ITO) having different surface resistivities. A second, similarly configured substrate can be provided and may be spaced apart from the first substrate by a dielectric spacer.

Abstract: A method for manufacturing a touch screen sensor assembly that includes providing a first transparent substrate, depositing a first non-metallic conductive layer onto the first substrate, removing the first conductive layer from a viewing portion of the first substrate, depositing a second non-metallic conductive layer onto the viewing portion, and removing portions of the second and first conductive layers to respectively form a first electrode pattern and a plurality of traces. The disclosed method also includes providing a second transparent substrate, depositing a third non-metallic conductive layer onto a viewing portion of the second substrate, removing portions of the third conductive layer to form a second electrode pattern, and bonding the first substrate to the second substrate using an optically clear adhesive. Each trace on the first substrate formed from the first conductive layer is electrically coupled to at least one electrode of either the first or second electrode patterns.

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract: The method for maximizing an unavailability interval includes the steps of initializing the starting frame number of each power saving class fi to 1 and adjusting fi to fi? when the least common multiple of m1, m2, . . . , mi?1 and mi is not relatively prime. The index i is an integer from 1 to t, mi is the sleep cycle of the ith power saving class, and fi? is an integer that maximizes common sleep windows of the i power saving classes. The common sleep windows of the t power saving classes are then set as the maximum unavailability interval of the wireless telecommunication device.

Abstract: The invention provides 3-carboxypropyl-aminotetralin compounds of formula (I): wherein R1, R2, R3, R4, R5, and R6 are defined in the specification, or a pharmaceutically-acceptable salt thereof, that are antagonists at the mu opioid receptor. The invention also provides pharmaceutical compositions comprising such compounds, methods of using such compounds to treat conditions associated with mu opioid receptor activity, and processes and intermediates useful for preparing such compounds.

Abstract: A method for constituting identification code utilized in a wireless human input device includes the following steps. Step A is to save a predetermined identification code in a non-electrical memory of a wireless human receiving device. Step B is that the wireless human transmitting device sends a packet contained an identification code with the same value as the predetermined identification code to the wireless human receiving device during the wireless human transmitting device being first time set up. The identification code is automatically generated by micro controller of the wireless human transmitting device. Step C is that the wireless human receiving device receives the packet in step B.

Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

Abstract: The invention provides 3-carboxypropyl-aminotetralin compounds of formula (I): wherein R1, R2, R3, R4, R5, and R6 are defined in the specification, or a pharmaceutically-acceptable salt thereof, that are antagonists at the mu opioid receptor. The invention also provides pharmaceutical compositions comprising such compounds, methods of using such compounds to treat conditions associated with mu opioid receptor activity, and processes and intermediates useful for preparing such compounds.