Abstract: A system includes a storage device and a processor. The storage device is configured to store a first set of values of TCP options for a first group of servers. The processor is configured to: transmit first requests to the first group of servers; receive first replies, in response to the first requests, from the first group of servers; determine the first set of values of the TCP options for the first group based on values in the first replies; store the first set of values in the storage device; receive a first message from a client to establish a connection between the client and a server in the first group of servers, and transmit, in response to the first message, a second message to the client.

Abstract: A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

Abstract: A light extraction film laminated to a glass substrate for organic light emitting diode (OLED) devices. The light extraction film includes a flexible substantially transparent film, a low index nanostructured layer applied to the film, and a high index planarizing backfill layer applied over the nanostructured layer. A glass substrate is laminated to the flexible substantially transparent film on a side opposite the nanostructured layer and including an ultra-low index region between the film and the glass substrate. The ultra-low index region is used to reduce optical losses occurring with the glass substrate.

Abstract: An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias.

Abstract: Flow monitoring tasks are assigned to a set of switches in a split architecture network to optimize network-wide flow monitoring. The assignment maximizes the number of monitored flows and reduces overhead of the flow monitoring. A controller receives an estimated traffic volume for each path in the network. The controller calculates, for all of the switches and all of the paths, sampling fractions that maximize the number of the flows sampled by the switches. In response to a request for setting up a new flow to traverse one of the paths in the network, the controller assigns the new flow to one of the switches that are located on the one of the paths, based on the sampling fraction for the assigned switch and the one of the paths, the bandwidth constraint and the memory constraint.

Abstract: Thermoplastic polymeric sheets are rendered microporous and remain substantially flat by contacting the sheet with a first fluid composition that contains or more solvents for the polymeric sheet to render the sheet microporous and then contacting the microporous sheet with a second fluid composition that is substantially free of solvents for the polymer and that contains a non-solvent that is miscible with the one or more solvents of the first composition. Contacting the microporous sheet with the second fluid composition preferably occurs prior to substantial evaporation of the first fluid compositions, or solvents thereof, from the microporous sheet.

Abstract: A method for implementing a general packet radio service (GPRS) tunnel protocol (GTP) in a packet core (PC) of a third generation (3G) network having a split architecture where a control plane of the PC of the 3G network is in a cloud computing system, the cloud computing system including a controller, the controller to execute a plurality of control plane modules, the control plane to communicate with the data plane of the PC through a control plane protocol, the data plane implemented in a plurality of network elements of the 3G network by configuring switches implementing a data plane of the SGSN and GGSN and intermediate switches to establish a first and second GTP tunnel endpoint.

Abstract: The present invention provides N6-substituted adenosine derivatives and N6-substituted adenine derivatives, manufacturing methods thereof, a pharmaceutical composition comprising the said compounds above, and uses of these compounds in manufacturing medicaments and health-care products for treating insomnia, convulsion, epilepsy, and Parkinson's diseases, and preventing and treating dementia.

Abstract: A method is implemented in a network element that functions as one of a plurality of controllers for one of a plurality of areas of a split architecture network. The controller provides a control plane for the area of the split architecture network where the controller is remote from a plurality of switches providing a data plane for the area of split architecture network. The controller facilitates optimized routing across the plurality of areas of the split architecture network by providing limited intra-area link cost data to other controllers of other areas of the split architecture network and to traditional routers of a network including the split architecture network. The limited intra-area link cost data provides costs of each possible shortest path traversal of the area of the controller without providing all internal link cost data.

Abstract: A system and method for aligning maps using polyline matching is provided. A global map and a local map are represented as polyline maps including a plurality of line segments. One or more approximate matches between the polyline maps are identified. One or more refined matches are determined from the approximate matches. The global map and the local map are aligned at the one or more refined matches.

Abstract: The invention is a routing algorithm characteristic that minimizes the weight, meaning that the probability that a node is disconnected from the controller in case of a failure in the network is minimized. The first algorithm used in the invention is an approximation algorithm for finding the controller routing tree that provides maximum resilience in the network. The algorithm is referred to herein as the Maximum Resilience (MR) algorithm. The heuristic MR algorithm selects a shortest-path tree as a starting point and modifies the tree in order to improve resilience. The output of the MR algorithm is not necessarily a shortest-path tree, but provides more resilience compared to the initial tree. The RASP algorithm provides a shortest-path tree with improved network resilience compared to other possible shortest-path trees.

Abstract: A method and apparatus for optimizing the resilience of a network using a combination of in-band and out-of-band signaling is disclosed. The metric used in the embodiment's algorithm to determine resilience is the maximum number of protected neighbors. Nodes closer to the controller are assigned a higher weight than those further from the controller because if their connection to the network is interrupted, all their downstream nodes will be affected and disconnected. Therefore, when determining a path to the controller, switches with alternate paths to the controller are preferred. Dedicated connections using out-of-band signaling are assigned to convert unprotected nodes to protected nodes thus improving the resilience of the network.

Abstract: A method implemented by a network topology design system, the network topology design system including a processing device. The method to determine placement of a controller within a network with a split architecture where control plane components of the split architecture network are executed by a controller and the control plane components are separate from data plane components of the split architecture network.

Abstract: A network topology design system to determine placement of a set of controllers within a network with a split architecture, the placement of the set of controllers selected to minimize disruption of the split architecture network caused by a link failure, a switch failure or a connectivity loss between the set of controllers and the data plane components. The system performs a method including graphing a topology of the split architecture network, determining a set of clusters of nodes within the graph by applying an agglomerative clustering process or a partitive clustering process, determining, a centroid for each cluster in the set of clusters, assigning one of the set of controllers to each network element corresponding to a determined centroid in the graph, and assigning each controller to control a set of network elements corresponding to a cluster in the graph.

Abstract: Mouse monoclonal antibodies specifically recognizing the Penicillin Binding Protein 2a (PBP2a) derived from a strain of Methicillin-Resistant Staphylococcus aureus (MRSA) were produced and characterized. The immunogen used to generate an immune response in a mouse was a PBP2a recombinant protein derived from a strain of Methicillin-Resistant Staphylococcus aureus (MRSA). The data showed that both monoclonal antibodies of the disclosure were able to distinguish MRSA from MSSA bacteria. The monoclonal antibodies have distinct recognition patterns for the regions of the PBP2a protein sequence. Epitope mapping has localized regions of the PBP2a protein specifically recognized by one or both of the monoclonal antibodies. The monoclonal antibodies of the present disclosure having the ability to distinguish between MRSA and MSSA strains can be useful as the basis for a diagnostic assay useful in the clinical setting for determining whether and which antibiotics to administer to a patient.

Abstract: The present invention provides a method for preparing modified micronized particles, comprising the steps of carrying out co-precipitation in an aqueous solution at a temperature between the freezing point and the boiling point of the reaction mother liquid to produce a mixed precipitate of micronized particles or precursors thereof and an inorganic precipitate. The method effectively solves the conflict between micronization and surface modification of particles, and resolves the problem that it is difficult to separate micronized particles from the reaction mother liquid.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

Abstract: A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Abstract: A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.

Abstract: A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.