Abstract: A method for controlling operation of a receiver may include: generating an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, wherein N is a natural number, of a hopping pattern included in a preamble of a packet; and controlling whether an Nth symbol of each hopping pattern included in a header or payload of the packet may be processed in response to the operation control signal. A receiver may include: an operation control signal generator that may generate an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, where N is a natural number, of a hopping pattern included in a preamble of a packet; and a receiving unit that may control whether an Nth symbol of each hopping pattern included in a header or payload of the packet is processed in response to the operation control signal.

Abstract: Provided is a composition for cancer treatment including phytosphingosine or a derivative thereof, or a pharmaceutically acceptable salt thereof as an active ingredient.

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

Abstract: A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.

Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Abstract: A method of testing a semiconductor device, which can reduce a period of time for testing a packaged semiconductor chip. First, semiconductor chips to be tested are classified in a lot unit. The semiconductor chips are fist tested in units of lots. The defective semiconductor chips among the semiconductor chips of a predetermined number of lots that are first time tested are collectively retested. First test data regarding the semiconductor chips may be classified and stored for each respective lot. Retest data regarding the semiconductor chips may be classified and stored for each respective lot. Test data regarding the semiconductor chips may be classified and stored into first test data and retest data for each respective lot.

Abstract: A logic gate includes a first driver connected to a first power source, a first control transistor connected between a first node and a second power source to control a voltage of the first node, a second driver connected between a gate electrode of the first control transistor and the second power source, a third driver connected between the first power source and the second power source, a second control transistor connected between the third driver and the second power source, and having a first electrode connected to an output terminal, and a fourth driver arranged between a gate electrode of the second control transistor and the second power source, wherein the first control transistor, the second control transistor and each transistor of the first driver, the second driver, the third driver and the fourth driver are PMOS transistors.

Abstract: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.

Abstract: A write strategy method, medium, and apparatus. The method includes writing a signal to a storage medium by using a predetermined power and an initial write strategy, calculating variation characteristics of a data signal which separately correspond to variations of write strategy parameters, if the written signal does not satisfy initial quality standards, and calculating correlations among periods of the data signal and correlations among the write strategy parameters by using the variation characteristics of the data signal, and determining the write strategy parameters based on the correlations among the periods of the data signal and the correlations among the write strategy parameters.

Abstract: Disclosed is a piezoelectric ink jet printer head in which a chamber and an ink storage are integrally formed. A process for manufacturing the ink jet printer head is also disclosed.

Abstract: An organic light emitting display configured to be driven using a frame divided into a plurality of sub-frames includes a data driver configured to supply a plurality of data signals to output lines during a first period of one horizontal period of the sub-frame, a scan driver configured to sequentially supply a scan signal to scan lines during a second period of the one horizontal period of the sub-frame, a demultiplexer coupled to each output line, the demultiplexer being configured to supply the data signals to a plurality of data lines, buffers configured to supply buffers supplying signals from the demulitplexers to the data lines, the buffers including PMOS transistors, and pixels disposed at intersections of the scan lines and the data lines, the pixels being configured to display images corresponding to the data signals.

Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

Abstract: An integrated circuit package system including a ribbon bond interconnect is provided, having a semiconductor device with at least one pad thereon. An external connection is provided. A heavy ribbon is provided and bonded to the external connection and to the pad on the semiconductor device.

Abstract: A method for continuous ethylene polymerization under high pressure using a polymerization reaction zone comprises a primary reaction zone and a secondary reaction zone wherein the secondary reaction zone has a length of 1.5-6.5 times the length of the primary reaction zone and a cross-sectional area of 1.2-4 times the cross-sectional area of the primary reaction zone. Ethylene is fed continuously into the primary reaction zone at the starting point of the primary reaction zone. Low temperature initiator alone, or an initiator mixture containing mainly low temperature initiator is introduced into the primary reaction zone at the starting point of the primary reaction zone. Initiator alone or an initiator mixture is introduced into the secondary reaction zone at two or more different points of the secondary reaction zone. Ethylene polymer products of various physical properties are produced with high productivity, while the pressure drop is minimized.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Abstract: In a pixel circuit of an organic EL display device, a gate of a driving transistor is coupled to a gate of a compensating transistor, which is configured to operate as a diode. A precharge voltage is applied to the gate of the driving transistor while a selection signal is applied to a previous scan line, so that the compensating transistor is biased in a forward direction to apply a data voltage on the gate of the drive transistor. The driving transistor may be electrically isolated from the organic EL element (OLED) while precharging, so as to prevent the OLED from emitting a light using the precharge voltage. In addition, the driving transistor may be electrically isolated from the OLED while the data voltage is being charged, so as to prevent the OLED from emitting a light.

Abstract: An organic light emitting display, suitable for a high quality and high resolution display device, rapidly charges a data voltage using a voltage programming technique, after compensating for a deviations in the threshold voltage and mobility of a driving transistor using a current programming technique.

Abstract: A pixel of a simplified configuration, and an organic light emitting display using the same are disclosed. The pixel includes an organic light emitting diode; a first transistor connected with a scan line and a data line and turned on when a scan signal is supplied to the scan lines; a storage capacitor having one terminal connected to an electrode of the first transistor and the other terminal connected to a reset line; and a second transistor for controlling an electric current that flows from a first power source to a second power source through the organic light emitting diode according to a voltage charged in the storage capacitor, wherein the second transistor is turned-off when a reset signal is supplied to the reset line.