Abstract: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.

Abstract: A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

Abstract: A keyboard-input information-security apparatus and method are provided.

Abstract: A circuit board including an embedded decoupling capacitor and a semiconductor package thereof are provided. The circuit board may include a core layer including an embedded decoupling capacitor, a first build-up layer at one side of the core layer, and a second build-up layer at the other side of the core layer, wherein the embedded decoupling capacitor includes a first electrode and a second electrode, the first build-up layer includes a first via contacting the first electrode, and the second build-up layer includes a second via contacting the first electrode.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes at least one memory bank including a plurality of memory cells and a self-refresh controller configured to generate a refresh address and to output a row address for a page to be refreshed based on the refresh address. The semiconductor memory device drives the at least one memory bank based on the row address and selectively refreshes pages in the at least one memory bank in response to the row address.

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract: A charging apparatus including a charging tube which has an outer surface contacting a photoconductive medium and electrically charges a surface of the photoconductive medium, a shaft which is disposed in the charging tube and to which a charging voltage is applied, and a conductive member which is connected to the shaft and contacts an inner surface of the charging tube. A friction coefficient between the conductive member and the inner surface of the charging tube may be less than a friction coefficient between the photoconductive medium and the outer surface of the charging tube, so that a slip phenomenon of the charging tube is prevented.

Abstract: A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate through the conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

Abstract: A high-voltage sawtooth current driving circuit and a memory device including the same are described. In the high-voltage sawtooth current driving circuit includes a charge pump circuit configured to output a first voltage, a regulating circuit configured to regulate a second voltage using the first voltage output from the charge pump circuit, and a sawtooth current driver configured to generate a sawtooth current in response to the second voltage regulated by the regulating circuit.

Abstract: In order to perform local dimming, a driving dimming duty cycle is generated using a target gamma curve (TGV), wherein the driving dimming duty cycle corresponds to a representative grayscale value (RGV) of each of a plurality of dimming unit areas. Each of a plurality of light unit blocks of a light source is driven based on the driving dimming duty cycle, wherein the light unit blocks correspond to the dimming unit areas, respectively. Therefore, a display apparatus may display an image having a higher contrast ratio than normal.

Abstract: A multiple compartment container having a plurality of independent double compartment containers within a container. Each double compartment container have an outer larger compartment fully enclosing an inner smaller compartment with each adjacent compartment having an independent open end located opposite each other to allow free accessibility to the compartment. Each open end accommodates a closure device to close the compartments. This prevents the contents of one compartment from mixing with the contents of the other compartment.

Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract: An apparatus and a method of performing radio communication are provided. The radio communication apparatus may determine a channel capacity of a radio channel based on a sensing duration to sense the radio channel and a false alarm probability, determine a sensing duration value and a false alarm probability value that maximize the channel capacity, and sense the radio channel based on the determined sensing duration value and the false alarm probability value.

Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Abstract: The present invention relates to a method for preparing capecitabine and a method for preparing a ?-anomer-rich trialkyl carbonate compound used therein, and a highly pure capecitabine can be efficiently prepared with a high yield by the method of the present invention using the ?-anomer-rich trialkyl carbonate compound as an intermediate.

Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.