Abstract: Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

Abstract: An apparatus for controlling black stretch includes a black stretching unit, an offset adjusting unit and an output unit. The black stretching unit performs black stretch processing on a video signal less than or equal to the maximum value of a black stretch control range in response to a slope of black stretch. The slope of black stretch corresponds to a region between a minimum value and a maximum value of the black stretch control range. The offset adjusting unit adjusts an offset of the black-stretched video signal. The output unit outputs an output video signal corresponding to the offset-adjusted video signal when the offset-adjusted video signal has a positive value in a region less than or equal to the minimum value, and outputs the output video signal corresponding to 0 when the offset-adjusted video signal has a negative value in the region less than or equal to the minimum value.

Abstract: The present invention relates to a preparation method for a biodegradable polymer microparticle and a microparticle prepared by the method. More particularly, the present invention relates to a method for preparing a polymer microparticle, wherein the method includes the steps of: dissolving a biodegradable polyester-based polymer in DMSO (Dimethyl Sulfoxide); spraying the solution in a low temperature hydrocarbon solution to provide a frozen DMSO microparticle; adding the microparticle in a low temperature salt aqueous solution to dissolve DMSO; and removing salt. The present invention provides a method for preparing a novel polymer microsphere which can be injected through a syringe due to excellent physical properties (such as biocompatibility, biodegradability, porosity, mechanical strength) and the microcarrier's size-adjustability, and can be easily mass-produced.

Abstract: A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Abstract: A display apparatus with at least two light guide plates, each including a light incident surface and a light exiting surface, the light guide plates being spaced apart from each other so as to form a gap therebetween. The display apparatus also has a light source disposed adjacent to at least one side portion of the light guide plates to emit light to the light incident surface, a display panel positioned to receive light from the light exiting surfaces to facilitate display of an image, and a diffusion member. The diffusion member covers the gap, so as to diffuse light directed toward the display panel.

Abstract: A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell. A detection reference point is changed upon wear indication to detect the resistance of the resistive memory cell. The resistance of the resistive memory cell is detected using the changed detection reference point to determine whether or not the resistive memory cell is worn by comparing the detected resistance to a wear reference level.

Abstract: A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.

Abstract: A vertically stacked fusion semiconductor device includes a channel portion which extends in a first direction with respect to a surface of a semiconductor layer, a common source line which extends in a second direction different from the first direction and is electrically connected to the channel portion, a first gate structure which is electrically connected to the common source line via the channel portion and a second gate structure which is electrically connected to the common source line via the channel portion and is on an opposite side of the common source line to the first gate structure.

Abstract: Disclosed is an apparatus and a method for signal transmission and reception according to a pre-processing scheme in a MIMO mobile communication system. The method includes: inputting a symbol; and pre-processing the input symbol according to a pre-processing matrix corresponding to pre-processing matrix information and transmitting the pre-processed symbol through a corresponding transmission antenna, wherein the pre-processing matrix is determined in accordance with a number of transmission antennas and a rate used in the MIMO mobile communication system.

Abstract: The present invention relates to a method and system for performing a handover from a serving base station to a target base station.

Abstract: A plurality of gray-scale values is extracted from image signals corresponding to a dimming area to calculate a mean value of the gray-scale values, and at least one of a variance, a standard deviation, a kurtosis, a skewness, a central moment, and an image moment is calculated using the mean value. Then, a representative gray-scale value corresponding to the dimming area is determined using the calculated values, and a dimming function for the light sources included in the dimming area is determined based on the representative gray-scale value. Then, the light sources included in the dimming area are driven based on the dimming function.

Abstract: Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection voltage, a row selection circuit configured to drive the non-selected word lines based on at least the first non-selected voltage, and a control logic circuit configured to control the voltage generator and the row selection circuit, such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells.

Abstract: A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.

Abstract: An apparatus and method for performing sequential scheduling in a multiple-input, multiple-output (MIMO) system is provided. The method includes the steps of: selecting a user which reports the greatest partial feedback information among a plurality of pieces of partial feedback information of all users in an initialization operation, and requesting channel feedback information to the selected user; and broadcasting the channel feedback information of the selected user to remaining unselected users upon receiving the channel feedback information from the selected user. Accordingly, a maximum capacity can be obtained by using only selective channel feedback information without having to feed back channel state information of all users.

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.

Abstract: Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.

Abstract: Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.

Abstract: A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.

Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.