Abstract: Disclosed herein is a light guide panel for a backlight unit of a liquid crystal display (LCD). The light guide panel enables adjustment in viewing angle and brightness at a specific position and angle by controlling a cross-sectional shape of front prisms of the light guide panel.

Abstract: A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.

Abstract: Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.

Abstract: Disclosed is a method for regulating terminal voltage of a cathode during overdischarge. Also disclosed is a lithium secondary battery, which is low in capacity loss after overdischarge, having excellent capacity restorability after overdischarge and shows an effect of preventing a battery from swelling at a high temperature.

Abstract: An exemplary embodiment of the present invention discloses a backlight unit with a plurality of light-emitting blocks and a light source driving section. The plurality of light-emitting blocks are arranged in a matrix shape along first and second directions different from each other. Each of the light-emitting blocks includes a light source unit having at least one light-emitting chip to emit light, and a light guiding unit to guide the light. The light source driving section controls the light source unit of the light-emitting blocks to drive the light source unit. Therefore, a thickness of the backlight unit may be reduced.

Abstract: The present application describes a method of diagnosing gastric cancer or a stage in the progression of the cancer in a subject comprising assaying for loss of expression of a marker gene such as POPDC3, CCDC67, LRRC3B, PRKD1, CYP1B1, LIMS2, DCBLD2, LOC149351, ADCY8, BACH2, ALOX5, TCF4, CXXC4, CAMK2N2, EMX1, KCNK9, NCAM2, AMPD3, NOG, SP6, LOC100128675, or CHSY3, or a combination thereof.

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract: Provided is a secondary battery comprising a cathode active material having low-electrolyte wettability as a main ingredient, which is capable of improving high-rate discharge properties by an addition of a perfluorinated sulfonamide substituent-containing polymer (“additive”) to a cathode mix and/or an electrolyte.

Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

Abstract: A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path.

Abstract: A light guide panel includes a lateral side configured to transmit light to an interior of the light guide panel, a rear side configured to reflect light to the interior of the light guide panel, and a front side configured to emit light from the interior of the light guide panel, wherein the rear side includes a repeating pattern of regions, each region having a plurality of wedge-shaped rear prisms disposed therein, and the wedge-shaped rear prisms include at least one of a side having a predetermined radius of curvature and a side having a point of inflection.

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract: An organic light emitting display and method of fabricating the same are provided. The organic light emitting display includes: a TFT disposed on a substrate and having a gate electrode and source and drain electrodes; a pixel electrode formed on a planarization layer having a via contact hole over the substrate, connected to one of the source and drain electrodes through the via contact hole, and having an etching surface extending to the planarization layer; a pixel defining layer pattern for defining an emission region formed on the entire surface; an organic layer formed on an emission region of the pixel electrode, and having at least an emission layer; and an opposite electrode formed on the entire surface, thereby preventing the organic layer from being separated from an edge of the pixel electrode and a short circuit from occurring between the pixel electrode and the opposite electrode to improve device characteristics and reliability.

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A method of compensating a photo sensor (and a corresponding photo sensor with compensation) insures the accuracy of the photo sensor, e.g., over environmental variations or photo cell variations. The method comprises: providing a first signal indicative of a light level; providing a second signal indicative of an environmental parameter, e.g., temperature; and calculating, responsive to the first signal and the second signal, a compensated signal that is indicative of an absolute light level. The calculating can be performed by a processor and utilize calibration and compensation information or parameters, which can be obtained experimentally.

Abstract: In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

Abstract: A light guide plate includes a main body having opposing side faces, and front and rear faces connected to the opposing side faces, the front face being adapted to output light incident on at least one of the side faces, a plurality of front prisms disposed at the front face of the main body, and a plurality of dot prisms disposed in an array at the rear face of the main body, the dot prisms being spaced apart from each other, each of the dot prisms including prism parts, sizes of the dot prisms increasing as a distance from the at least one side face increases.

Abstract: The present invention relates to a piezoelectric linear motor that can make relatively low abrasion and accurate linear movement since stationary AC voltages are applied to two piezoelectric elements with a phase difference. The present invention provides a piezoelectric linear motor, comprising: a piezoelectric substrate having a first piezoelectric element and a second piezoelectric element, wherein AC voltages are applied to the first and second piezoelectric elements with a phase difference; a metallic elastic body having first and second elastic bodies coupled to the piezoelectric elements and a central protrusion protruded at the central portion connecting the first and second elastic bodies, wherein the central protrusion oscillates elliptically during an application of the voltage; and a mover brought into contact with the central protrusion of the metallic elastic body for a linear movement, and wherein the movement of the mover is orthogonal to the central protrusion.

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g.