Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: Disclosed herein is a decay heat removal system, including: a decay heat exchanger that absorbs decay heat generated by a nuclear reactor; a heat pipe heat exchanger that receives the decay heat from the decay heat exchanger through a sodium loop for heat removal and then discharges the decay heat to the outside; and a sodium-air heat exchanger that is connected to the heat pipe heat exchanger through the sodium loop and discharges the decay heat transferred thereto through the sodium loop to the outside. According to the decay heat removal system, a heat removal capability can be realized by the heat pipe heat exchanger at such a high temperature at which the safety of a nuclear reactor is under threat, and a cooling effect can be obtained through the sodium-air heat exchanger at a temperature lower than that temperature.

Abstract: A data processor receives sets of input image data having respective input grays and outputs sets of output image data having respective output grays. Each set of output image data corresponds to one of the plurality of sets of input image data and have more image data than each set of the input image data. A data driver supplies the pixels with data voltages corresponding to the output image data supplied from the data processor. A set of output grays corresponding to a set of input grays are selected from sets of grays, each set of grays giving an average front transmittance substantially equal to an average front transmittance of the set of input grays. The sets of output grays generate the closest average lateral gamma curve generated by the sets of grays relative to an average front gamma curve generated by the input grays.

Abstract: The present invention relates to a backlight unit that includes at least one first light emitting diode (LED) package and at least one second LED package, wherein the first LED package includes a blue LED chip, a green LED chip, and a first phosphor, the first phosphor being excited by blue light and to emit light to be mixed with blue light and green light respectively emitted from the blue LED chip and the green LED chip, the first LED package to thereby emit white light; the second LED package includes a blue LED chip, a red LED chip, and a second phosphor, the second phosphor being excited by blue light and to emit light to be mixed with blue light and red light respectively emitted from the blue LED chip and the red LED chip, the second LED package to thereby emit white light; and the first LED package and the second LED package are alternately arranged.

Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A flash memory device and a related method of write protecting data are disclosed. The flash memory device includes a protection controller having a latch circuit storing temporary protected/accessible data, a cell array storing persistent protected/accessible data, a write controller altering the persistent protected/accessible data, and a latch controller altering the temporary protected/accessible data.

Abstract: A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.

Abstract: A TFT having a dual buffer structure, a method of fabricating the same, and a flat panel display having the TFT, and a method of fabricating the same are provided. The TFT includes a first buffer layer formed of an amorphous silicon layer on a substrate, a second buffer layer formed on the first buffer layer. The TFT also includes a semiconductor layer formed on the second buffer layer and a gate electrode formed on the semiconductor layer. The dual buffer structure provides better barrier to impurities diffusing from the substrate, and also acts as a black matrix to reduce unwanted reflections and is a source of hydrogen to passivate other layers.

Abstract: Provided is a switched capacitor resonator including at least one integrator circuit having a differential operational amplifier and a sub feedback circuit configured with a switched capacitor circuit. A main feedback circuit connecting main input and output terminals of the switched capacitor resonator to each other may be configured with the switched capacitor circuit. The main feedback circuit may be connected to the sub feedback circuit included in one of the integrator circuits. A capacitor of the main feedback circuit can serve as an integration capacitor connected between the input and output terminals of the differential operational amplifier. Consequently, it is possible to improve an operating speed by reducing a settling time constant of the integrator circuit.

Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Abstract: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a corresponding threshold voltage of the first data state, and verifying results of the successive programming.

Abstract: Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1st through n?1th sub program data, n being a natural number greater than 2.

Abstract: A light guide plate includes a light incident surface for receiving light, first and second light emission surfaces for emitting light at a first light emission angle with respect to the first and second light emission surfaces, and a light reflection pattern formed on the first light emission surface, for reflecting the light toward the second light emission surface. The reflected light from the light reflection pattern exits the second light emission surface at a second light emission angle with respect to the second light emission surface, and the second light emission angle is larger than the first light emission angle. The light reflection pattern includes multiple dots each having a prim pattern on their surface and light reflecting surfaces elongated in a selected direction. The adjacent light reflecting surfaces meet each other at their elongated edges to form a prism shape.

Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer.

Abstract: Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

Abstract: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

Abstract: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.