Abstract: Provided is signaling transmitting and receiving methods, device, network-side device, terminal and storage medium. The signaling transmitting method includes: determining a first parameter set and/or a second parameter set for N resource groups; and transmitting an indication signaling, the indication signaling carries indication information for indicating the first parameter set and/or the second parameter set. The signaling receiving method includes: receiving an indication signaling transmitted by a network-side device. The indication signaling carries indication information for indicating a first parameter set and/or a second parameter set determined by the network-side device for N resource groups. The first parameter set is a Physical Downlink Shared Channel Resource Element (PDSCH RE) mapping set. The second parameter set is a Quasi-Co-Location (QCL) parameter set. N is a positive integer greater than 1.

Abstract: A front cover assembly includes a frame, a cover glass, and a waterproof glue. The frame has a receiving cavity. The cover glass is partially received in the frame. The cover glass has a lateral face facing the frame. The cover glass has a step portion located at the lateral face. A first gap is defined between a first face of the step portion of the cover glass and a first wall of the frame, and a second gap is defined between a second face of the step portion of the cover glass and a second wall of the frame. A waterproof glue fills the first and second gaps. The first and second faces of the step portion from an obtuse angle therebetween, which faces the first and second walls of the frame. The present disclosure also relates to a terminal.

Abstract: An approach for deploying workload in a multi-tenancy computing environment is provided. The approach generates, by one or more computer processors, a tenant ID and a plan ID for a tenant based, at least in part, on a tenant registration request. The approach stores, by one or more computer processors, the tenant ID and the plan ID into a shared system record. The approach receives, by one or more computer processors, a request to update a first tenant service plan. The approach determines, by one or more computer processors, one or more resource pools supporting a second tenant service plan based at least in part, on an association between the tenant ID and the plan ID. The approach deploys, by one or more computer processors, one or more resources from the one or more resource pools supporting the second tenant service plan.

Abstract: A method for fabricating a Fin-FET device includes forming fin structures on a substrate and an isolation structure to cover a portion of sidewall surfaces of the fin structures, forming gate structures to cover a portion of sidewall and top surfaces of the fin structures, forming doped source/drain regions in the fin structures, forming a metal layer on the doped source/drain regions and the gate structures, performing a reaction annealing process to convert the metal layer formed on the doped source/drain regions into a metal contact layer and then removing the unreacted metal layer, forming a dielectric layer on the metal contact layer and the gate structures with a top surface higher than the top surfaces of the gate structures, forming a plurality of vias through the dielectric layer above the metal contact layer, and forming a plurality of conductive plugs by filling the vias.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a base substrate including a first region and a second region; and forming a first doped region in the first region, and a second doped region in the second region. The second doped region is doped with blocking ions. The method also includes forming a first metal layer on a surface of the first doped region and on a surface of the second doped region; and forming a second metal layer on a surface of the first metal layer. The second metal layer is made of a material different from the first metal layer. Further, the method includes forming a first metal silicide layer and a second metal silicide layer by performing an annealing process. The blocking ions block atoms of the second metal layer from diffusing into the second metal silicide layer.

Abstract: An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate regions with each pass-gate transistor including a second gate structure. A portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions. Moreover, the concentration of the first doping ions is less than the concentration of the second doping ions, and the work function of the first work function layer in the first gate structures is greater than the work function of the second work function layer in the second gate structures.

Abstract: A dual-camera module assembly includes a first flexible printed circuit (FPC), a second FPC, a first camera module and a second camera module. The first FPC includes a first body and a first connecting end, the first body being connected to the first camera module. The second FPC includes a second body, and an extension portion and a second connecting end sequentially extending from the second body, the second body being connected to the second camera module, the extension portion and the first body are arranged in a superposition manner. The first connecting end and the second connecting end are connected to a main circuit board. A smallest one of distances from the first connecting end to an antenna clearance zone of the main circuit board and distances from the second connecting end to the antenna clearance zone is greater than or equal to a predetermined value.

Abstract: An electric motor has a wound stator and an outer rotor. A core of the stator has outer and inner annular portions. Tooth portions extend radially outwardly from the outer annular portion. Connecting arms interconnect the outer and inner annular portions. The width of the connecting arms is less than the width of the tooth portions. The ratio of tooth height L1 to distance between the roots of adjacent teeth L3 is in the range of 1.0 and 1.3. The ratio of tooth width T3 to L3 is in the range of 0.8 and 1.0. The ratio of tooth length T1 to L3 is in the range of 0.5 and 0.6. The ratio of T3 to outer diameter of the stator core D is in the range of 0.07 and 0.1.

Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an N-type logic region including a first and a second N-type threshold voltage region, a P-type logic region including a first and a second P-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an N-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer.

Abstract: An electric motor has stator with a core of magnetic material, a winding frame covering the core and windings wound around the winding frame. The core has an annular yoke and a plurality of teeth that extend radially outwardly from the yoke. The winding frame is an overmolded structure and has an insulation part that covers the core, a supporting part disposed inward of the insulation part and a plurality of ribs that connect the insulation part and the supporting part. A reinforcing ring is embedded in the supporting part. The strength of the reinforcing ring is higher than the strength of the winding frame. Thus material utilization is improved and the weight of the stator is reduced while ensuring the strength of the supporting part.

Abstract: A parallel data processing method based on multiple graphic processing units (GPUs) is provided, including: creating, in a central processing unit (CPU), a plurality of worker threads for controlling a plurality of worker groups respectively, the worker groups including one or more GPUs; binding each worker thread to a corresponding GPU; loading a plurality of batches of training data from a nonvolatile memory to GPU video memories in the plurality of worker groups; and controlling the plurality of GPUs to perform data processing in parallel through the worker threads. The method can enhance efficiency of multi-GPU parallel data processing. In addition, a parallel data processing apparatus is further provided.

Abstract: Disclosed are a channel state information (CSI) based processing method, and a terminal, a base station and a computer storage medium. The method comprises: a terminal acquiring channel measurement process configuration information, wherein at least one CST process configuration includes configuring M sets of channel state information reference symbols (CSI-RSs) for channel measurement, with M being an integer greater than or equal to 1; and the terminal determining m sets of CSI-RSs for CSI measurement, wherein the m sets of CSI-RSs are a sub-set of the M sets of CSI-RSs, with m being an integer.

Abstract: A static random-access memory (SRAM) device includes a base substrate including a PU transistor region and a PD transistor region adjacent to the PU transistor region, a gate dielectric layer formed on a portion of the base substrate in the PU transistor region and the PD transistor region, a first WF layer formed on a portion of the gate dielectric layer in the PU transistor region and a second WF layer formed on the first WF layer in the PU transistor region, and a third WF layer formed on a top surface and a sidewall surface of the second WF layer in the PU transistor region, a sidewall surface of the first WF layer in the PU transistor region, and the gate dielectric layer in the PD transistor region. Each of the first WF layer and the second WF layer is made of a P-type WF material, and the third WF layer is made of an N-type WF material. The SRAM device also includes a gate electrode layer formed on the third WF layer.

Abstract: The present invention provides a single phase permanent magnet motor including a stator core and a permanent magnet rotor. The stator core includes an end portion and two arm portions extending from the end portion. Each arm portion includes a connecting arm connected to the end portion and a pole claw formed at a distal end of the connecting arm. The two pole claws defines a receiving space. The rotor is rotatably disposed in the receiving space of the stator core. The rotor includes a rotor core made of a magnetic material and at least one permanent magnet attached to the rotor core.

Abstract: A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an NMOS region and a PMOS region; forming a first high-K gate dielectric layer on the NMOS region of the substrate; forming an interfacial layer on the PMOS region of the substrate; forming a second high-K gate dielectric layer on the interfacial layer and the first high-K gate dielectric layer; forming a metal layer on the second high-K gate dielectric layer.

Abstract: A method and apparatus for generating a reference signal sequence for performing channel estimation. In one embodiment, the method includes: determining an initialization value; limiting the initialization value to be less than a predetermined positive integer M to provide a limited initialization value; mapping the limited initialization value into an initialization sequence having a predetermined number L of sequence values; providing the initialization sequence to a pseudo-random number generator to generate a pseudo-random number sequence; and generating the RS sequence based on the PRNS.

Abstract: A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Abstract: A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region. The method also includes forming a gate structure on each fin; and forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region. In addition, the method includes forming a first pull-down doped region connected to an adjacent pull-up doped epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region. Further, the method includes forming a second pull-down doped region by performing an ion-doped non-epitaxial layer process on the fin on another side of the gate structure in the pull-down transistor region.

Abstract: The present invention discloses a lamp, mounted on a socket when in use, comprising a cap, a housing, and a light source, wherein the cap is adapted to connect to the socket, one of the cap and the housing comprises a tubular body, and the other comprises a cylindrical cavity for accommodating the tubular body, and the tubular body rotates in the cylindrical cavity around an axis of the cap and moves along the axial direction of the cap to effect relative rotation and relative telescopic motion between the cap and the housing. The lamp of the present invention allows both relative rotation and relative telescopic motion between the cap and the housing, therefore facilitating adjustment of the illumination direction, and is adaptable to different types of fittings.

Abstract: An operation mechanism of a circuit breaker includes: a tripping component; a left side plate; a right side plate; a latch; a half shaft; a lever; and a main shaft. The tripping component, the latch, the half shaft and the lever are mounted between the left side plate and the right side plate. The half shaft and the main shaft penetrate through the left side plate and the right side plate, and extend out of the left side plate and the right side plate. The lever includes a sheet metal bending piece. The sheet metal bending piece is bent to form a top wall and two side walls. The tripping component, the latch, the half shaft, the lever and the main shaft move in linkage. The tripping and the latch form a two-level latch. The operation mechanism of the circuit breaker is manual operation.