Abstract: A two-level latch mechanism for an operation mechanism of a circuit breaker is provided. The operation mechanism includes: a tripping component, a left side plate, a right side plate, a latch, a half shaft, a lever, and a main shaft. The tripping component, the latch and the lever are mounted between the left side plate and the right side plate. The half shaft and the main shaft penetrate through the left side plate and the right side plate, and extend out of the left side plate and the right side plate. The tripping component, the latch, the half shaft, the lever, and the main shaft move in linkage. The tripping component includes a tripping buckle and a latch surface is disposed on a second end of the tripping buckle. The tripping component, the latch component and the half shaft component form a two-level latch.

Abstract: The present invention relates to a light emitting diode (LED) lamp, which includes: a base configured to electrically connect with an external power supply; at least one first printed circuit board (PCB), with at least one LED mounted thereon; a driver module, electrically connected to the base and the first PCB, and configured to drive an LED; a heat dissipation module, thermally contacted with the first PCB, and configured to dissipate heat generated from the LED; a connecting device, connected to the heat dissipation module; and a replaceable active cooling module, detachably connected to the connecting device, and configured to generate a cooling fluid for cooling at least one of the PCB and the heat dissipation module.

Abstract: The present disclosure is directed to a semiconductor device and a manufacturing method therefor. In one implementations, a method includes: providing a semiconductor structure, where the semiconductor structure includes: a substrate, and a first fin and a second fin spaced on the substrate; depositing a first interlayer dielectric layer on the semiconductor structure; performing first partial etching on the first interlayer dielectric layer to expose a top of the first fin; after the top of the first fin is exposed, removing a part of the first fin to form a first groove; epitaxially growing a first electrode in the first groove; performing second partial etching on the first interlayer dielectric layer to expose a top of the second fin; after the top of the second fin is exposed, removing a part of the second fin to form a second groove, where the second groove is separated from the first groove; and epitaxially growing a second electrode in the second groove.

Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a base substrate; forming doped epitaxial layers in the base substrate on sides of a gate structure on the base substrate; forming an interlayer dielectric layer over the base substrate and above the doped epitaxial layers; forming a contact opening in the interlayer dielectric layer; forming a dielectric layer on and surrounding each doped epitaxial layer; applying a repairing process on the dielectric layer; after the repairing process, forming a metal layer on the dielectric layer; and after forming the metal layer in the contact opening, forming a conductive plug in the contact opening.

Abstract: A method for fabricating an SRAM device includes providing a base substrate including a pull up transistor (PUT) region and a pull down transistor (PDT) region, forming a gate dielectric layer, forming a first work function (WF) layer using a P-type WF material, removing the first WF layer formed in the PDT region, forming a second WF layer using a P-type WF material on the first WF layer in the PUT region and on the gate dielectric layer in the PDT region, removing the second WF layer formed in the PDT region, forming a third WF layer using an N-type WF material on the top and the sidewall surfaces of the second WF layer in the PUT region, the sidewall surface of the first WF layer in the PUT region, and the gate dielectric layer in the PDT region, and forming a gate electrode layer on the third WF layer.

Abstract: A semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming a first dielectric layer on the base substrate; forming a target gate structure in the first dielectric layer and on the base substrate, where a first groove is formed above the target gate structure and in the first dielectric layer; forming a second groove by etching the first dielectric layer on sidewalls of the first groove to expand an opening of the first groove; forming a protective layer in the second groove; and forming conductive plugs in the first dielectric layer on sides of the target gate structure and the protective layer. The protective layer has a dielectric constant greater than the first dielectric layer.

Abstract: An electrostatic discharge protection structure and a fabricating method thereof are provided. The electrostatic discharge protection structure comprises: a substrate; multiple fin portions arranged on the substrate; a gate structure on the substrate across the fin portions, and on a portion of top surfaces and sidewalls of the fin portions; a first groove in the substrate and overlapping with a first extension pattern of the fin portions; a first doped epitaxial layer filled within the first groove, and being used as a source; a second groove in the substrate and overlapping with a second extension pattern of the fin portions; and a second doped epitaxial layer filled within the second groove, and being used as a drain.

Abstract: A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Abstract: The present invention is directed to processes for preparing beta 3 agonists of Formula (I) and Formula (II) and their intermediates. The beta 3 agonists are useful in the treatment of certain disorders, including overactive bladder, urinary incontinence, and urinary urgency.

Abstract: Provided are a method for channel information feedback in a multi-antenna system, and a terminal. The method comprises: a terminal receives CSI-RSs of M ports sent by a base station, and performs estimation according to the CSI-RSs to obtain M-dimensional downlink channel information; the terminal uses a transformation function Fk to perform a linear transformation on the M-dimensional downlink channel information, and obtains Nk-dimensional kth type channels, wherein k is greater than or equal to 1 and less than or equal to K, M?Nk, and K?1; the terminal uses a preset Nk-dimensional codebook to respectively perform channel information quantisation on the kth type channels, and determines a corresponding precoding matrix and precoding matrix indicator information (PMIk); the terminal selects S type channels from within K type channels, and feeds index numbers of the selected channels and corresponding PMI back to the base station.

Abstract: Examples described herein relate to enhancing data communication performance in a wireless communication network including a first subscription associated with a first radio access technology (RAT) and a second subscription associated with a second RAT, where the wireless communication device uses a same radio frequency (RF) resource to communicate over both the first RAT and the second RAT. The first RAT is used, in part, for data operations while the second RAT is used, in part, for voice operations. During idle state voice operations, the RF resource is reallocated from performing data operations to performing idle state voice operations, causing interruptions in the data operations. The wireless communication device adjusts at least one or a duration and an occurrence of the idle state voice operations to reduce the impact on the data operations.

Abstract: A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an NMOS region and a PMOS region adjacent to the NMOS region; forming an N-type well in the PMOS region and a P-type well in the NMOS region of the substrate; forming a protective sidewall to cover an upper portion of a sidewall surface of each fin in each of the NMOS region and PMOS region and to expose a lower portion of the sidewall surface of each fin; removing a partial width of the lower portion of the fin using the protective sidewall as an etch mask; removing the protective sidewall; and forming an isolation structure at least by oxidizing the remaining lower portion of the fin and having a top surface lower than the neighboring upper portions of the fins.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate; forming a source and a drain that are at least partially located in the substrate; forming a diffused layer on a surface of at least one of the source or the drain, where a conductivity type of the diffused layer is the same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain; and performing an annealing processing after the diffused layer is formed. The present disclosure can increase a doping density at a surface of a source and/or a drain, helping to reduce a contact resistance, thereby improving performance of a device.

Abstract: Disclosed is a coffee powder compressing device for a coffee maker, comprising an accommodating chamber (11a); a filter assembly (17); a movable pressing block (5); a first sealing ring (6); and a brewing chamber (B) formed by the first sealing ring (6), the movable pressing block (5) and the filter assembly (17); an extrusion portion (5a) being disposed on the lower end of the movable pressing block (5), when the movable pressing block (5) is situated at the second position and the filter assembly (17) is located into the accommodating chamber (11a), the extrusion portion (5a) inserts into the cavity (12a); thereby, by means of compressing the coffee powder through the extrusion portion (5a), solving the problem that the tightness of the compressed coffee powder is difficult to be controlled and the laborious problem in the existing coffee powder pre-compressing methods.

Abstract: Aspects of the present disclosure relate to receiver beamforming for serving and neighbor cell measurements. An exemplary method generally includes communicating with one or more base stations using a first beam type, initiating a transition to communicating with at least one of the one or more base stations using a second beam type in response to an indication of a trigger event, and communicating with the at least one of the one or more base stations using the second beam type.

Abstract: A bracket assembly for use in a mobile terminal includes a metal support and a multi-contact spring. The metal support is configured to support an electronic component of the mobile terminal. The multi-contact spring includes a first pressure contact part, a second pressure contact part, a first elastic part, a second elastic part, and a fixing part. The multi-contact spring is fixed to a frame of the mobile terminal by a fastener extending through the fixing part into the frame. The first elastic part is connected to the first pressure contact part and the fixing part and is configured to provide a first restoring force to the first pressure contact part such that the first pressure contact part abuts against a metal cover of the mobile terminal and is grounded.

Abstract: A method for fabricating a semiconductor device includes providing a base substrate, forming a plurality of doped regions in the base substrate, forming an initial capping layer covering surfaces of the plurality of doped regions, forming a dielectric layer on the initial capping layer and the base substrate, forming a plurality of vias in the dielectric layer to expose a surface portion of the initial capping layer, and etching the exposed surface portion of the initial capping layer at a bottom of each via to form a silicide region exposed at the bottom of the via. The silicide region has a reduced thickness compared with a thickness of the initial capping layer. The method further includes forming a metal silicide layer by performing a self-aligned silicide process on an entire silicide region. The metal silicide layer is in contact with the plurality of doped regions.

Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and a surface portion of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.

Abstract: A flyback converter control architecture is provided in which primary-only feedback techniques are used to ensure smooth startup and detection of fault conditions. During steady-state operation, secondary-side regulation is employed. In addition, current limits are monitored during steady-state operation using primary-only feedback techniques to obviate the need for a secondary-side current sense resistor.

Abstract: A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.