Abstract: A semiconductor device includes a substrate, a semiconductor fin on the substrate, an isolation region on sidewalls of the semiconductor fin and having an upper surface lower than an upper surface of the semiconductor fin, a gate structure on a portion of the semiconductor fin and on a first portion of the isolation region. The portion of the semiconductor fin covered by the gate structure is referred to as a first region, and a second portion of the isolation region disposed on at least one of two opposite sides of the gate structure is referred to as a second region, which has an upper surface lower than an upper surface of the first region. The semiconductor device also includes a first spacer layer on a sidewall of the gate structure and on a sidewall of a portion of the first region disposed above the second region.

Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.

Abstract: The disclosure discloses a virtual impedance comprehensive control method for an inductive power filtering (IPF) system. According to the disclosure, harmonic damping control at grid side and zero impedance control of filters are organically combined according to a technical problem which is unsolved and process difficulty in equipment manufacturing in an existing filtering method, so that the problem of performance reduction of passive filtering equipment caused by a change in an impedance parameter of a power grid system is solved on one hand, optimization control over a quality factor of the passive filtering equipment may be implemented to reduce dependence on an equipment production process level on the other hand, a quality factor of the single-tuned filters may meet a design requirement, and an overall filtering characteristic is further improved.

Abstract: A VTFET device and fabrication method is provided. The method includes: forming a first doped layer on a semiconductor substrate. Vertical nanowires are formed on the first doped layer. Dummy gate layers are formed on the first doped layer, and a first interlayer dielectric layer is formed on a top surface of the first doped layer exposed by dummy gate layers. Grooves are formed in the first interlayer dielectric layer, by removing a portion of the first interlayer dielectric layer and removing a partial thickness of the vertical nanowires. A second doped layer is formed in each groove. Openings are formed by etching the first interlayer dielectric layer between adjacent vertical nanowires, to expose the dummy gate layers. The dummy gate layers are removed through the openings to form cavities and each cavity includes the opening and a space provided by the removed dummy gate layers.

Abstract: The invention provides a method of transmitting a sounding reference signal (SRS) and a device utilizing the same. The method comprises: a user equipment transmits, to a base station, a sounding reference signal (SRS) on a time domain symbol in a special subframe, wherein the time domain symbol comprises one or more time domain symbols of time domain symbols occupying an uplink pilot time slot; and a number of the time domain symbols occupying the uplink pilot time slot is N, N is an integer, and 3?N?12. The embodiment resolves a problem of an incomplete scheme of transmitting an SRS on a time domain symbol, and realizes transmission of an SRS on increased time domain symbols.

Abstract: The invention provide a control method, including: obtaining a time division scheme of a STA in a next cruise monitoring period, where the next cruise monitoring period includes N adjustment periods and N monitoring periods determined by means of division according to N preset points; configuring control information according to the time division scheme, where the control information is for controlling an operating status of the STA in each adjustment period in the next cruise monitoring period; and sending the control information to the STA.

Abstract: A semiconductor device and fabrication method are provided. The method includes providing a first dielectric layer with a first groove on a base substrate. A first gate electrode is formed in the first groove, with a top surface lower than the first dielectric layer. A first protective layer is formed on a portion of the top surface of the first gate electrode, with a first oxygen ionic concentration. A compensating protective layer is formed on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, with a second oxygen ionic concentration. A second dielectric layer is formed on the first protective layer, on the compensating protective layer, and on the first dielectric layer, with a third oxygen ionic concentration. The first oxygen ionic concentration and second oxygen ionic concentration are smaller than the third oxygen ionic concentration.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate including isolation regions and a device region between adjacent isolation regions; forming a plurality of fin structures, including a first plurality of fin structures on the isolation regions and a second plurality of fin structures on the device region of the substrate; forming an isolation layer, having a top surface lower than top surfaces of the fin structures, on the substrate between adjacent fin structures; etching the first plurality of fin structures on the isolation regions after forming the isolation layer; and forming a gate structure across the second plurality of fin structures on the device region after etching the first plurality of fin structures formed on the isolation regions. The gate structure covers a portion of sidewall and top surfaces of each fin structure of the second plurality of fin structures on the device region.

Abstract: A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

Abstract: An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate regions with each pass-gate transistor including a second gate structure. A portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions. Moreover, the concentration of the first doping ions is less than the concentration of the second doping ions, and the work function of the first work function layer in the first gate structures is greater than the work function of the second work function layer in the second gate structures.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

Abstract: The present disclosure is directed to methods and system for managing communication of packets. A transceiver node receives a plurality of IP data packets from an internet protocol (IP) network. The transceiver node separates the IP data packets into a first set and a second set of IP data packets, according to channel conditions of a cellular network and a wireless local area network (WLAN). The transceiver node transmits, to a user device, the first set of IP data packets using a cellular network protocol of the cellular network and the second set of IP data packets using a WLAN protocol of the WLAN, causing the user device to aggregate the first set of IP data packets transmitted using the cellular network protocol with the second set of IP data packets transmitted using the WLAN protocol.

Abstract: Embodiments of the present invention disclose a method, relay agent and system for acquiring an IP address in a network. According to the method, the relay agent configures multiple gateway IP addresses corresponding to a type of a client, adds the multiple gateway IP addresses to a DHCP Discover packet of the client, and sends the DHCP Discover packet to a DHCP server, so that the DHCP server allocates an IP address to the client, and sends a DHCP Offer packet to the client after determining that one gateway IP address in the multiple gateway IP addresses belongs to a same network segment as the allocated IP address, so that the DHCP server allocates the IP address to the client, thereby implementing that multiple IPs in different IP address segments are allocated to a same DHCP client type.

Abstract: The embodiments of the invention provide a method of configuring a channel state information reference signal (CSI-RS) transmitted on a pilot and a device utilizing the same. The method includes: a base station generates a signaling including configuration information of a CSI-RS; and the base station transmits the signaling including the configuration information of the CSI-RS; wherein the configuration information includes a CSI-RS port number, CSI-RS resource patterns and a CSI-RS subframe configuration; the CSI-RS resource patterns include at least one of the following: CSI-RS resource patterns transmitted on a normal downlink subframe and CSI-RS resource patterns transmitted on a downlink pilot time slot (DwPTS). The CSI-RS subframe configuration includes a CSI-RS subframe configuration transmitted on both the DwPTS and the normal downlink subframe.

Abstract: The present disclosure provides a method and device for configuring a channel state information reference signal (CSI-RS), and a method and device for parsing CSI-RS. The configuration method includes: configuring configuration information of the CSI-RS by a base station; generating a signaling carrying the configuration information of the CSI-RS by the base station; and transmitting the signaling by the base station. The configuration information includes at least one of: a number of CSI-RS ports, a number K of components of a pilot resource pattern, a number N of ports of the components of the pilot resource pattern, and a CSI-RS port-sorting mode, where the CSI-RS port-sorting mode includes M types of candidate port-sorting mode, and M, K, and N are positive integers.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a plurality of fins on the substrate, a hardmask layer on the fins, and a first insulating layer on the substrate for isolating the fins. The first insulating layer has an upper surface substantially flush with an upper surface of the hardmask layer. The method also includes etching back the first insulating layer to form a second insulating layer having an upper surface lower than a bottom surface of the hardmask layer, performing an oxidation process or an annealing process on the second insulating layer, removing the hardmask layer after performing the oxidation process or the annealing process, and etching back the second insulating layer to form an insulating region having an upper surface lower than an upper surface of the fins.

Abstract: A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

Abstract: A system controls a transmission of a sequence of compressed video data from an encoder buffer to a network for delivery to a decoder buffer. Control of the transmission includes to: determine characteristics of a video transmission path between the encoder buffer and the decoder buffer, the characteristics comprising at least one of a buffer size of the decoder buffer, an input rate of the decoder buffer, and a buffer size of an equivalent intermediary buffer of the video transmission path; determine a transmission rate from the characteristics of the video transmission path and from the sequence of compressed video data, the transmission rate being determined such that a target quality of service value can be guaranteed for the entire sequence of compressed video data transmitted at the determined transmission rate to the decoder buffer; and control transmission of the sequence of compressed video data at the determined transmission rate.

Abstract: The invention encompasses a novel process for making piperidinone carboxamide indane and azainane derivatives, which are CGRP receptor antagonists useful for the treatment of migraine.

Abstract: A single phase brushless motor includes a stator and a rotor. The stator includes a stator core and stator windings wound on the stator core. The stator core includes a yoke portion, and first and second pole portions extending inwardly from the yoke portion. An end surface of the first pole portion includes a first arc surface having a first groove. An end surface of the second pole portion includes a second arc surface having a second groove. The first and second arc surfaces are opposed to each other and define a receiving space therebetween. The rotor includes a rotary shaft and permanent magnetic poles fixed to the rotary shaft. The permanent magnetic poles are received in the receiving space. A substantially uniform gap is formed between the first arc surface and the second arc surface and the permanent magnetic poles.