Abstract: The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.

Abstract: The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

Abstract: The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.

Abstract: A method of manufacturing a strained semiconductor substrate includes the steps of provide a Si substrate and depositing a strained Si1-xGex layer on the Si substrate. The Si substrate and strained Si1-xGex layer are subjected to rapid thermal annealing which forms a relaxed Si1-xGex layer on the Si substrate. The method further includes the steps of depositing a buffer Si1-xGex layer on the relaxed Si1-xGex layer, and depositing Si on the buffer Si1-xGex layer. The buffer Si1-xGex layer causes the deposited Si to form a strained Si layer on the buffer Si1-xGex layer with the combined layers forming the strained semiconductor substrate.

Abstract: Disclosed is a single-phase motor including a stator, a rotor adapted to rotate when electric power is applied to the stator, a ring-shaped magnet coupled to the rotor to rotate along with the rotor; a parking magnet for stopping the rotor within an effective torque generating region by a magnetic force effected between the ring-shaped magnet and the parking magnet upon braking the rotor, and a sensor unit for sensing a variation in the intensity of a magnetic field generated around the ring-shaped magnet during the rotation of the rotor, thereby sensing the position and speed of the rotor. In accordance with this configuration, the additional device used for an initial driving operation and subsequent operations of the motor can be relatively simple and inexpensive. As a result, there is an advantage in that the motor has an enhanced utility.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: The present invention discloses a prosthetic implant and an insertion instrument for inserting the prosthetic implant between adjacent vertebrae. The prosthetic implant in accordance with the present invention includes a housing for being packed with bone chips, an inserting hole formed at a first end of the housing, through which an insertion instrument can be inserted, and a connection recess formed on inner surface of the housing around the inserting hole, on which the insertion instrument is stably placed. The insertion instrument in accordance with the present invention includes a connection member having a connection chip at a first end, a rotating means for rotating and returning the connection member at a predetermined angle. In accordance with the present invention, the insertion instrument can be separated from the prosthetic implant by rotation of only one time after the prosthetic implanted is completely inserted, so that the operation process of implanting the prosthetic implant is easy and safe.

Abstract: Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.

Abstract: The present invention is related to a stack gate electrode capable of suppressing a formation of a non-uniform silicide layer at an interface between a polysilicon layer and a metal layer during a selective oxidation process and a thermal process both being performed after a gate patterning process and a method for fabricating a semiconductor device including the same. The stack gate electrode includes: a silicon layer; a reaction prevention layer formed on the silicon layer, wherein the reaction prevention layer containing nitrogen and silicon has a surface density of nitrogen above about 1×1015/cm2; and a metal layer formed on the reaction prevention layer.

Abstract: The present invention relates to a method for forming a landing plug capable of securing a low resistance by employing a selective epitaxial growth technique to meet demands of high-integration and high-speed in a semiconductor device. The method includes the steps of: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer until exposing a partial portion of the substrate; forming a first conductive layer with a predetermined thickness inside of the contact hole, the first conductive layer being made of a silicon layer; forming a second conductive layer on the inter-layer insulation layer in such a manner of being buried into the contact hole in which the silicon layer is formed; and performing a blanket etch process to the second conductive layer until exposing surfaces of the inter-layer insulation layer and the hard mask so that a landing plug is formed.

Abstract: The present invention provides a method for forming multiple gate oxide layers with different thickness in one chip by using a simple process. Particularly, a series of processes such as the first oxidation, the nitridation, the wet dip-out and the second oxidation contribute to form the gate oxide layer having different thicknesses. As a result, it is possible to integrate those various devices having different driving voltages into one chip. It is further possible to manufacture diverse products with improvements on layout design and device and process margins.

Abstract: Disclosed is a single-phase motor including a stator, a rotor adapted to rotate when electric power is applied to the stator, a ring-shaped magnet coupled to the rotor to rotate along with the rotor; a parking magnet for stopping the rotor within an effective torque generating region by a magnetic force effected between the ring-shaped magnet and the parking magnet upon braking the rotor, and a sensor unit for sensing a variation in the intensity of a magnetic field generated around the ring-shaped magnet during the rotation of the rotor, thereby sensing the position and speed of the rotor. In accordance with this configuration, the additional device used for an initial driving operation and subsequent operations of the motor can be relatively simple and inexpensive. As a result, there is an advantage in that the motor has an enhanced utility.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: The present invention discloses a prosthetic implant and an insertion instrument for inserting the prosthetic implant between adjacent vertebrae. The prosthetic implant in accordance with the present invention includes a housing for being packed with bone chips, an inserting hole formed at a first end of the housing, through which an insertion instrument can be inserted, and a connection recess formed on inner surface of the housing around the inserting hole, on which the insertion instrument is stably placed. The insertion instrument in accordance with the present invention includes a connection member having a connection chip at a first end, a rotating means for rotating and returning the connection member at a predetermined angle. In accordance with the present invention, the insertion instrument can be separated from the prosthetic implant by rotation of only one time after the prosthetic implanted is completely inserted, so that the operation process of implanting the prosthetic implant is easy and safe.

Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

Abstract: The invention provides a method of preparing chitin films and novel chitin films produced by the method of the invention. In the invention, chitin solution is coagulated to form a gel which is then pressed to form a film. The film, still under press is further processed to remove residual solvent and the film is then washed. An absorbent-matrix may be introduced into the chitin solution to form a swellable film and the invention also provides a method of preparing an absorbent-matrix by mixing two or more polymer solutions to form a precipitate, dispersion or coacervate which is then isolated and dried to form the absorbent matrix.

Abstract: A fusion cage adapted for promoting fusion of bone grafts or bone substitutes packed in the fusion cage with the adjoining vertebrae, wherein the fusion cage has a shape of cylindrical closed U of which upper and lower ends are opened such that an internal cavity is defined by a plane rear wall, both sidewalls, and a rounded front wall. An upper and lower ends of each sidewall are roundly swollen so as to secure enough contact with an upper and lower surfaces of the adjoined vertebrae.

Abstract: CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below.

Abstract: The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.