Abstract: A semiconductor package includes a first semiconductor chip having a first semiconductor chip body including a first circuit region and peripheral regions arranged around the first circuit region. A first bonding pad group is arranged within the first circuit region and includes a plurality of bonding pads. A first redistribution group including a plurality of redistributions is electrically connected to the respective bonding pads and extends towards the peripheral regions. The package further includes a second semiconductor chip having a second semiconductor chip body including a second circuit region opposing the first circuit region. A second bonding pad group is arranged within the second circuit region and corresponds to the first bonding pad group. A second redistribution group is electrically connected to the respective bonding pads of the second bonding pad group. Redistribution connection members are used to electrically connect the first redistribution group to the second redistribution group.

Abstract: A display apparatus having a ground bracket. The display apparatus includes a display panel, which displays an image, a filter, which includes an electromagnetic shielding layer and is directly attached to a first surface in which the image of the display panel is formed, and a chassis, which is disposed on the side of a second surface, which is an opposite surface of the first surface, of the display panel and supports the display panel. The ground bracket includes a conductive material, in which a first wing portion is electrically connected to the electromagnetic shielding layer of the filter, a second wing portion which is electrically connected to the chassis, and the first and second wing portions substantially face each other, and a pressing device, which is installed in the ground bracket and presses the first and second wing portions of the ground bracket in the direction the first and second wing portions are facing. Accordingly, an electromagnetic shielding performance of the filter is improved.

Abstract: A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer.

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract: A receiver comprises two tuners and a DC-to-DC converter (DCC) for generating an increased supply voltage (VH) on the basis of a main supply voltage. Each tuner comprises a tunable circuit (TUC1), which can be tuned by means of a tuning voltage (VT1). Each tuner further comprises a tuning control circuit (TCC1) that is coupled to the DC-to-DC converter (DCC) via a load circuit (LD1) for generating the tuning voltage (VT1). The load circuit (LD1) of at least one of the two tuners comprises a branch (D1) coupled to receive the main supply voltage (VCC). The branch (D1) is conductive when the tuning voltage (VT1) is within a voltage range substantially comprised between 0 and the main supply voltage (VCC).

Abstract: Provided are an apparatus and method of dividing virtual sites using policy properties in multiprotocol label switching (MPLS) networks. In this method, when multiple virtual sites are selected with respect to one interface, not only usually used source IP addresses and VLAN tags but also TOS fields and MPLS labels are used so that more various kinds of virtual sites can be selected. Also, since the TOS fields and MPLS labels can express additional QoS-related information, differentiated services can be provided by selecting a wider variety of kinds of virtual sites.

Abstract: A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.

Abstract: The present invention discloses an SAW sensor device using a slit acoustic wave and a method thereof. The SAW sensor device using the slit acoustic wave includes a piezoelectric medium having a thin membrane at its one portion, a medium at the other portion, and a narrow slit which the slit acoustic wave passes through at its inside, an input IDT formed at the outer portion in the narrow slit of the piezoelectric medium, for transducing an electric input signal into the slit acoustic wave, and an output IDT formed at the outer portion opposite to the input IDT, for receiving the propagated slit acoustic wave and transducing the wave into an electric signal, whereby an external pressure transmitted to the device is sensed.

Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.

Abstract: The subscriber station of claim 15, wherein the uplink data includes data to be transmitted, and a header having information on the data and the subscriber, and the uplink data generator adds the subheader includDisclosed is a method and device for requesting and reporting channel quality information in a mobile communication system. An uplink radio resource for a subscriber station having data to transmit is allocated and a CQI indicator for requesting channel quality information is added to the allocation information to be transmitted to a subscriber station. The subscriber station having received the uplink radio resource allocation information generates channel quality information by measuring the radio channel quality for communication with the base station according to existence of the indicator and transmits desired uplink data having the generated channel quality information to the base station.

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.

Abstract: Disclosed is a method for allocating and accessing downlink resources in the OFDMA communication system. In the resource allocation method, bursts having the same modulation and channel encoding level are arranged in a predetermined temporal order on a physical layer. Information on the allocated unit resources is included in a common control block and is transmitted to a subscriber station, and the subscriber station then detects a number of the allocated unit resources to thus check the range of bursts to be received by the subscriber station. Therefore, power consumption by the subscriber station is reduced and signaling overheads of the common control information and unneeded residual resources are decreased.

Abstract: A flat display panel in which a field emission principle of ferroelectrics is applied to improve the luminous efficiency with a low driving voltage, and a method of driving the same.

Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.

Abstract: An image sensor with sufficient photoelectric conversion capacity and enhanced reliability and a method of fabricating the same, in which the image sensor includes a bare substrate; an epitaxial layer disposed on the bare substrate and including a first impurity distribution region of a first conductivity type, which is formed on the bare substrate, and a second impurity distribution region of a second conductivity type, which is formed on the first impurity distribution region; and a charge collection well formed within the epitaxial layer and at least partially doped with third impurities of the second conductivity type, wherein the charge collection well occupies the first impurity distribution region and the second impurity distribution region and represents the second conductivity type as a whole.

Abstract: The present invention relates to a device for controlling a state of a terminal with respect to mobility management, and a method thereof. The state of the terminal includes a disconnected state and a connected state, the connected state includes an active state and an idle state, and the active state includes an active sub-state and a standby sub-state. The terminal in the active state updates location information for each cell, and the terminal in the idle state updates the location information for each radio access network registration area including a plurality of cells. The terminal in the active sub-state performs a handover when leaving a current cell. The terminal in the standby sub-state determines a quality of service (QoS) of packet data, and performs the handover or is set to be in the idle state according to the determined QoS.

Abstract: A single slope ADC using a hysteresis property includes a first comparator, a second comparator, and a code generating unit. The first comparator outputs a compared signal by receiving and comparing an input signal having a constant level with a ramp signal, the second comparator has a hysteresis property having an input terminal connected to an output terminal of the first comparator, and the code generating unit is connected to the second comparator and outputs a digital code corresponding to a time-point of a state transition of an output signal of the second comparator. The second comparator can be embodied as a Schmidt trigger or a Schmidt-trigger inverter. The single slope ADC further includes a controller that controls at least one of a rising threshold or a failing threshold of the Schmidt trigger or of the Schmidt-trigger inverter.

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer over a substrate, forming an intermediate structure over the first conductive layer, the intermediate structure formed in a stack structure comprising at least a first metal layer and a nitrogen containing metal silicide layer, and forming a second conductive layer over the intermediate structure.

Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.