Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7271066
    Abstract: Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: September 18, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan Yong Lim, Heung Jae Cho, Jung Ho Lee
  • Patent number: 7271879
    Abstract: A planar positioning system having a rigid base, and first and second linear actuator means mounted to the rigid base, the first and second linear actuator means being arranged orthogonal to one another. A rigid reference surface (2A, 2B) is mounted to the base, (1) and a moveable platform (17) for holding a workpiece is supported for movement on the rigid reference surface (2A, 2B). First and second guiding means are coupled to moveable portions of the respective first and second actuator means, the first and second guiding means being arranged to bear on the moveable platform for transmission of forces thereto from the respective first and second actuator means to effect movement of the platform (17) on said rigid reference surface (2A, 2B). The first actuator means may comprise two linear actuators (4A, 4B) parallel to one another and spaced apart with the second linear actuator means (8) orthogonal thereto and arranged in an H-shaped configuration.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: September 18, 2007
    Assignee: Agency for Science, Technology and Research
    Inventors: Ser Yong Lim, Wei Lin, Yong Peng Leow
  • Publication number: 20070200145
    Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.
    Type: Application
    Filed: April 30, 2007
    Publication date: August 30, 2007
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Yong-Soo Kim, Se-Aug Jang, Hyun-Chul Sohn
  • Patent number: 7256084
    Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: August 14, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang Choo Hsia, Young Way Teh, John Sudijono, Wee Leng Tan, Hui Peng Koh
  • Publication number: 20070148943
    Abstract: Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a WSixNy film or a WSix film by using an ALD process.
    Type: Application
    Filed: August 30, 2006
    Publication date: June 28, 2007
    Inventors: Soo Hyun Kim, Kwan Yong Lim, Baek Mann Kim, Young Jin Lee, Noh Jung Kwak, Hyun Chul Sohn
  • Patent number: 7233095
    Abstract: A single crystal substrate and a cutting method thereof are provided. The single crystal substrate includes a langasite substrate with a SAW propagation surface; and input and output IDTs having electrodes on the surface for launching and/or detecting surface acoustic waves, wherein a direction of surface wave propagation is parallel to an X?-axis, and the substrate farther has an Z?-axis perpendicular to the surface and a Y?-axis parallel to the surface and perpendicular to the X?-axis, the langasite substrate having a crystal orientation defined by modified axes X, Y and Z, the relative orientation of axes X?, Y? and Z? being defined by Euler angles ?, ? and ?, in which ? is in a range of 8°???25°, ? in a range of 15°???30°, and ? is in a range of 55°???85°.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: June 19, 2007
    Assignee: LG Innotek Co., Ltd.
    Inventors: Valentin Cherednick, Michail Dvoesherstov, Yong Lim Choi
  • Publication number: 20070123179
    Abstract: There is provided a slide hinge device for guiding a slide of a slide part on a main part. The slide hinge device includes: a slide hinge unit installed in the rear of the slide part, for guiding a slide of the slide part; a fixed hinge unit installed in the front of the main part; and a lift hinge unit rotatably installed to the fixed hinge unit and engaged with the slide hinge unit to guide a slide of the slide hinge unit. In the case the slide part is opened, the lift hinge unit rotates to the fixed hinge unit and raises the slide part to be slanted towards the main part, thereby enabling a microphone and a receiver of a personal portable device to be close to the mouth and an ear of a user, respectively.
    Type: Application
    Filed: June 30, 2006
    Publication date: May 31, 2007
    Inventor: Yong Lim
  • Patent number: 7217624
    Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 15, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Yong-Soo Kim, Se-Aug Jang, Hyun-Chul Sohn
  • Publication number: 20070066013
    Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.
    Type: Application
    Filed: June 8, 2006
    Publication date: March 22, 2007
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho, Hong-Seon Yang
  • Publication number: 20070045724
    Abstract: A gate pattern of a semiconductor device and a method for fabricating the same are provided. The gate pattern includes a substrate with a trench, a gate insulation layer, a first gate electrode layer and a second gate electrode layer. The gate insulation layer is formed over the substrate with the trench. The first gate electrode layer is buried into the trench not to be projected above the gate insulation layer. The second gate electrode layer is formed over the first gate electrode layer and has a predetermined portion contacting the first gate electrode layer.
    Type: Application
    Filed: February 24, 2006
    Publication date: March 1, 2007
    Inventors: Kwan-Yong Lim, Yun-Seok Chun, Hyun-Jung Kim, Min-Gyu Sung
  • Publication number: 20070045854
    Abstract: A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.
    Type: Application
    Filed: August 28, 2006
    Publication date: March 1, 2007
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho
  • Publication number: 20070010268
    Abstract: Information for different subscribers of a service with the same modulation and channel encoding method is transmitted by allocating radio resources in a wireless portable Internet system. Also, identifier information on the subscriber of a concurrently allocated radio resource is transmitted through common control information. Therefore, information for a plurality of subscribers coexists in a single radio resource block, and it can be easily transmitted. Since a subscriber station which has received downlink information can know to which radio resource block the information for the corresponding station is allocated through the subscriber identifier information transmitted as common control information, the subscriber station can access desired information by accessing a specific radio resource block to which information for the subscriber is allocated in the received frame.
    Type: Application
    Filed: July 16, 2004
    Publication date: January 11, 2007
    Inventors: Jae-Heung Kim, Soon-Yong Lim, Chul-Sik Yoon, Kun-Min Yeo, Seok-Joo Shin, Boong-Gee Song, Kwang-Seop Eom, Min-Hee Cho, Jae-Hee Cho, Byung-Han Ryu, Seung-Ku Hwang
  • Publication number: 20070004154
    Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.
    Type: Application
    Filed: November 2, 2005
    Publication date: January 4, 2007
    Inventors: Kwon Hong, Kwan-Yong Lim
  • Publication number: 20070001246
    Abstract: A gate electrode with a double diffusion barrier and a fabrication method of a semiconductor device including the same are provided. The gate electrode of a semiconductor device includes: a silicon electrode; a double diffusion barrier formed on the silicon electrode and including at least a crystalline tungsten nitride-based layer; and a metal electrode formed on the double diffusion barrier.
    Type: Application
    Filed: November 1, 2005
    Publication date: January 4, 2007
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho, Hong-Seon Yang, Seung-Ryong Lee
  • Patent number: 7157359
    Abstract: A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: January 2, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae Gyu Park, Heung Jae Cho, Kwan Yong Lim
  • Patent number: 7157339
    Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: January 2, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Dae-Gyu Park, Tae-Ho Cha, In-Seok Yeo
  • Patent number: 7145207
    Abstract: A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012 ° C.-dyne/cm2.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 5, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hong-Seon Yang, Se-Aug Jang, Yong-Soo Kim, Kwan-Yong Lim, Heung-Jae Cho, Jae-Geun Oh
  • Patent number: 7136299
    Abstract: A phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: November 14, 2006
    Assignee: BeyondMicro Inc
    Inventors: Eu Gene Chu, Ju Ho Mo, Seong Taek Park, Jung Ho Kim, Hyun Yong Lim, Pyeong Han Lee, Ja Choon Jeong
  • Publication number: 20060246669
    Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
    Type: Application
    Filed: June 28, 2006
    Publication date: November 2, 2006
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Dae-Gyu Park, Tae-Ho Cha, In-Seok Yeo
  • Publication number: 20060214584
    Abstract: A plasma display panel includes a first substrate and a second substrate that partially define a plurality of discharge cells in a space therebetween, and an electrode structure including an address electrode extending along a first direction, a dielectric layer formed on the address electrode, a first electrode extending along a second direction intersecting the first direction, and a second electrode extending along the second direction intersecting the first direction, where the first electrode and the second electrode are electrically insulated from the address electrode, and at least a portion of each of the first electrode and the second electrode is associated with each of the discharge cells. At least one of the address electrode and the dielectric layer associated with each of the discharge cells may include a first portion and a second portion.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 28, 2006
    Inventors: Min Hur, Jae-Yong Lim