Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: A wide dynamic range CMOS image sensor is invented for easily changing a photo-response characteristic between a linear response and a logarithmic response without altering any hardware. A method of controlling the photo-response characteristic is also provided in which: the reset signal generator of the CMOS image sensor sets the maximum value of a reset pulse to VDD and the minimum value of the reset pulse to ?V which is greater than VSS, such that the active pixel can have a photo-response characteristic that combines a linear response and a logarithmic response. When the ?V value is varied in the reset pulse generated from the reset signal generator, the boundary between the linear response and the logarithmic response of the image sensor can be adjusted.

Abstract: Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2eV and holes in a hole level disposed on the first electrode layer, and a second electrode layer disposed on the abrupt MIT semiconductor organic or inorganic material layer. An abrupt MIT is generated in the abrupt MIT semiconductor material layer by a field applied between the first electrode layer and the second electrode layer.

Abstract: Disclosed is the method of forming the gate in the semiconductor device. The present method can prevent abnormal oxidization and lifting at the interface of the stack gate consisting of polysilicon and a metal and can be applied to even the single metal gate, by replacing a re-oxidization process for recovering damage of the gate oxide film generated in the gate patterning process with the oxygen plasma treatment.

Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.

Abstract: A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012° C.-dyne/cm2.

Abstract: Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

Abstract: The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

Abstract: Provided are a plastic microfabricated structure, and a microfabricated thermal device, a microfabricated reactor, a microfabricated reactor array and a micro array using the same, which may be applied to a bio chip, and the present invention may fabricate the plastic microfabricated structure for providing a heating region by means of insulating plastic, which has a thin thickness, flatness enough to allow a photolithography process to be performed, thermal isolation in its some or total area, and a small thermal mass, and on top of the heating region of the plastic microfabricated structure, a heater, a temperature sensor for sensing a temperature, an electrode, and an electrode pad are formed to thereby fabricate the microfabricated heating device, whereby element may be readily fabricated at a low cost, and the heating region is formed of a plastic thin layer, so that uniform temperature control is possible even with a low power, and various samples may be thermally treated at a fast speed to obtain their

Abstract: Provided is a micro-fluidic heating system, which comprises a micro-fluidic control element for providing a chamber, a flow path and a valve, and a main body for heating the inside of the chamber in contact with the micro-fluidic control element, wherein the micro-fluidic control element consists of an upper substrate for providing the chamber, the flow path and the valve, and a lower substrate as a thin film bonded to the upper substrate, and the main body consists of a membrane in which heating means and suction holes are formed, and support member for supporting the membrane, and the heating means is partially in contact with the lower substrate of the chamber to heat the inside of the chamber, so that thermal transfer efficiency becomes maximized and temperature of each chamber may be independently controlled in the case of configuration having chambers arranged in array.

Abstract: Provided is a microfluidic control device and method for controlling the microfluid, and a fine amount of fluid is controlled even with natural fluid flow and solution injection, wherein a pressure barrier of a capillary is removed by a surface tension change resulted from the solution injection to thereby obtain transport, interflow, mixing, and time delay of the microfluid, and to detail this, solution is injected to meet the boundary surface of the stopped fluid when the fluid is stopped by the stop valve, so that a function of the stop valve is removed to obtain the transport, interflow, and mixing of the fluid, and the method for controlling the microfluid may be applied to the microfluidic control device for biochemical reaction, and it uses only the capillary force change resulted from solution injection to thereby have its structure simplified.

Abstract: Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

Abstract: The present invention relates to a method of providing a routing protocol in a sensor network. The routing protocol is a new model which is made considering a battery efficiency so that an AODV protocol, which is widely used because of its simplified and reliable algorithm, can be matched to a sensor condition. An energy information of a node is contained in the RREQ message of the AODV, thereby allowing the neighboring nodes and the nodes on the path to know their energy states.

Abstract: A current-jump-control circuit including an abrupt metal-insulator phase transition device is proposed, and includes a source, the abrupt metal-insulator phase transition device and a resistive element. The abrupt metal-insulator phase transition device includes first and second electrodes connected to the source, and shows an abrupt metal-insulator phase transition characteristic of a current jump when an electric field is applied between the first electrode and the second electrode. The resistive element is connected between the source and the abrupt metal-insulator phase transition device to control a jump current flowing through the abrupt metal-insulator phase transition device. According to the above current control circuit, the abrupt metal-insulator phase transition device can be prevented from being failed due to a large amount of current and thus the current-jump-control circuit can be applied in various application fields.

Abstract: Disclosed is a method for fabricating a semiconductor device with a polymetal gate electrode formed by a partial gate recessing process. The method includes the steps of forming a gate structure including a gate dielectric layer, a polysilicon layer, a metal layer, an etch stop layer and a sacrificial layer sequentially formed on a substrate; selectively performing a re-oxidation process to the gate structure; forming a spacer on each sidewall of the gate structure; implanting ions in the substrate for forming source/drain regions; selectively removing the sacrificial layer of the gate structure to form a recess; and filling an insulating hard mask into the recess for use in a self-aligned contact etching process.

Abstract: A ripple suppressor/compensator useful in the general area of motion control and applicable to a wide range of servomechanisms exhibiting a force ripple characteristics, including the permanent magnet linear motors. An adaptive feed-forward control signal is generated which compensates for the ripple force, thus allowing for more precise tracking performance to be achieved.

Abstract: Vasculature can be imaged with emissive semiconductor nanocrystals, for example, in the near infrared.

Abstract: A lymphatic system can be imaged with emissive semiconductor nanocrystals, for example, in the near infrared.

Abstract: The present invention relates to a method for patterning a metal wire of a semiconductor device capable of preventing an incidence of abnormal oxidation of a metal layer during a patterning of a gate electrode, a bit line or a metal lining as simultaneously as being capable of proceeding a lithography process easily. The method includes the steps of: forming stack layers having at least a metal layer as an upper most layer on a substrate; forming an anti-reflective coating layer on the stack layers by employing an atomic layer deposition technique; forming a photoresist pattern on the anti-reflective coating layer; patterning the anti-reflective coating layer by using the photoresist pattern as an etch mask; and forming a metal wire by etching the stack layers with use of the patterned anti-reflective coating layer as an etch mask.

Abstract: A planar positioning system having a rigid base, and first and second linear actuator means mounted to the rigid base, the first and second linear actuator means being arranged orthogonal to one another. A rigid reference surface (2A, 2B) is mounted to the base, (1) and a moveable platform (17) for holding a workpiece is supported for movement on the rigid reference surface (2A, 2B). First and second guiding means are coupled to moveable portions of the respective first and second actuator means, the first and second guiding means being arranged to bear on the moveable platform for transmission of forces thereto from the respective first and second actuator means to effect movement of the platform (17) on said rigid reference surface (2A, 2B). The first actuator means may comprise two linear actuators (4A, 4B) parallel to one another and spaced apart with the second linear actuator means (8) orthogonal thereto and arranged in an H-shaped configuration.