Abstract: A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.

Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

Abstract: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.

Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

Abstract: A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.

Abstract: A dynamic channel change technique is disclosed which may be implemented between nodes and a Head End of an access network. Initially a network device may communicate with the Head End via a first downstream channel and a first upstream channel. When the network device receives a dynamic channel change request which includes instructions for the network device to switch to a second downstream channel, the network device may respond by switching from the first downstream channel to the second downstream channel. Thereafter, the network device may communicate with the Head End via the second downstream channel and first upstream channel. Further, according to a specific embodiment, the dynamic channel change request may also include an upstream channel change request for causing the network device to switch from a first upstream channel to a second upstream channel.

Abstract: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.

Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

Abstract: The present invention provides a refresh controller for embedded DRAM, configured to receive an external access signal and generate refresh enabling signal REFN, refresh address signal CRA and confliction signal, said embedded DRAM comprising a plurality of memory groups, said controller comprising: a status controlling module that generates refresh enabling signal REFN and last refresh signal last_ccr according to the refresh interval and clock cycles; a refresh searching module that searches in said plurality of memory bank groups for at least one memory bank group that is to be refreshed in the refresh interval, and generates refresh address signal CRA according to the external access signal and the searched memory bank group; a scoreboard module that records the status of each of said plurality of memory bank groups according to said refresh address signal CRA and external access signal; and a confliction detecting module that generates confliction signal according to said external access signal, last ref

Abstract: A dynamic channel change technique is disclosed which may be implemented between nodes and a Head End of an access network. Initially a network device may communicate with the Head End via a first downstream channel and a first upstream channel. When the network device receives a dynamic channel change request which includes instructions for the network device to switch to a second downstream channel, the network device may respond by switching from the first downstream channel to the second downstream channel. Thereafter, the network device may communicate with the Head End via the second downstream channel and first upstream channel. Further, according to a specific embodiment, the dynamic channel change request may also include an upstream channel change request for causing the network device to switch from a first upstream channel to a second upstream channel.

Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

Abstract: An improved grid for a nuclear reactor fuel assembly that has an egg-crate base grid as the primary support structure with each support cell of the base grid that supports a fuel rod having a lock-support sleeve that is rotatable within the support cell between a first and second orientation. In the first orientation the lock-support sleeve fits loosely within the support cell of the base grid and respectively, loosely receives the fuel rods that are loaded therein. The lock-support sleeves are then rotated to a second orientation that locks the fuel rods axially within the support cells.

Abstract: Embodiments are provided to generate an integrated data structure. In an embodiment, a database system is configured to generate an integrated database view that includes a number of predicate-based objects and a number of enumerated objects. A declarative membership criteria can be used to provide automatic membership to a group of objects associated with the database system. A number of predicate-based group membership rules can be used when generating a database view that includes a number of predicate-based views and a number of enumerated groups.

Abstract: Aggregation of product data provided from external sources of product data for presentation on an e-commerce website. A set of product data related to a product that is offered for sale in e-commerce is accessed and subjected to an aggregation process. The set of product data is mapped for aggregation with other sets of product data based on an existing mapping or on an absence of an existing mapping. Access is provided to an aggregated set of product data that includes the set of product data that is mapped for aggregation with other sets of product data, for presentation on an e-commerce website.

Abstract: A microfibrous matrix with embedded supporting particulates/fibers and chemically reactive materials is provided as a filtration system for the removal of contaminants and other harmful agents from liquid and gaseous streams. Such materials may include chemically reactive materials as high surface area carbons, zeolites, silicas, aluminas, inorganic metal oxides, polymer resins, ZnO, ZnO/Carbon, Pt/?-Al2O3, PtCo/?-Al2O3, ZnO/SiO2 and various other catalysts, sorbents or reactants. The invention may be used to protect the intolerant anodes and cathodes of fuel cells from damaging H2S while simultaneously aiding the selective conversion of CO to CO2 in fuel streams predominated by hydrogen, to provide a highly efficient gas and/or liquid separation and purification methodology for gas masks, building filtration systems, and/or as polishing media located downstream of traditional packed bed filtration systems.

Abstract: A method and apparatus for configuring service groups in a cable network is provided. A method may comprise identifying a primary downstream channel in a cable network and identifying a plurality of fiber nodes fed by the primary downstream channel. For each fiber node identified, the method may comprise identifying a set of downstream channels communicating with the fiber node. If duplicate sets are identified, duplicate sets of downstream channels may be eliminated and a downstream service group may be associated with each of the remaining sets of downstream channels. In an example embodiment, at least one Media Access Control (MAC) domain is automatically selected to correspond to the identified service groups.

Abstract: Embodiments are provided to generate an integrated data structure. In an embodiment, a database system is configured to generate an integrated database view that includes a number of predicate-based objects and a number of enumerated objects. A declarative membership criteria can be used to provide automatic membership to a group of objects associated with the database system. A number of predicate-based group membership rules can be used when generating a database view that includes a number of predicate-based views and a number of enumerated groups.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated giant-magneto-resistive (GMR) structures. In an embodiment, a save-on-power-down circuit that may be integrated with conventional semiconductor-based computing, logic, and memory devices to retain volatile logic states and/or volatile digital information in a non-volatile manner is provided.