Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A display device including a first substrate including a display area that displays an image and a peripheral area, in which no image is displayed, surrounding the display area. The display device further includes a plurality of pixels disposed in the display area. The display device additionally includes a first metal layer disposed above the first substrate in the peripheral area, and the first metal layer including a plurality of openings. The display device further includes a sealant disposed above the first metal layer, and surrounding the plurality of pixels. The display device additionally includes a plurality of second metal layers disposed above the first substrate and below the first metal layer in the peripheral area, and respectively overlapping the openings of the first metal layer. A part of the sealant is disposed in the plurality of openings.

Abstract: A method of fabricating a memory device includes alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate, forming a channel hole by etching the insulating layers and the sacrificial layers to expose a partial region of the substrate, forming a channel structure in the channel hole, forming an opening by etching the insulating layers and the sacrificial layers to exposed a portion of the substrate, forming a plurality of side openings that include first side openings and a second side opening by removing the sacrificial layers through the opening, forming gate electrodes to fill the first side openings, and forming a blocking layer to fill the second side opening.

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

Abstract: An organic light emitting diode display includes a substrate, a semiconductor disposed on the substrate that includes a channel for each of a plurality of transistors and doping regions formed at both sides of each channel; a gate insulating layer disposed on the semiconductor that includes an insulating layer opening through which the doping regions of two different transistors are exposed; a gate electrode disposed on the gate insulating layer that overlaps each channel; an interlayer insulating layer disposed on the gate electrode that includes a first and second contact holes through which the doping regions exposed within the insulating layer opening are each exposed; and data wirings disposed on the interlayer insulating layer that are each connected to the doping regions. The interlayer insulating layer includes an organic layer, and the first and second contact holes each include a first side wall positioned within the insulating layer opening.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: Disclosed herein is an organic light emitting diode display, including: a first thin film transistor including a first active pattern positioned on the substrate and a first gate electrode positioned on the first active pattern; a third thin film transistor including a third active pattern connected to the other end of the first active pattern and a third gate electrode positioned on the third active pattern; and a gate bridge directly connecting between the third active pattern and the first gate electrode and positioned between the substrate and the third active pattern.

Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

Abstract: An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic conductive film including a binder resin; a curable alicyclic epoxy compound; a curable oxetane compound; a quaternary ammonium catalyst; and conductive particles, wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1: Heat quantity variation rate (%)=[(H0?H1)/H0]×100??Equation 1 wherein H0 is a DSC heat quantity of the anisotropic conductive film, as measured at 25° C. and a time point of 0 hr, and H1 is a DSC heat quantity of the anisotropic conductive film, as measured after being left at 40° C. for 24 hours.

Abstract: The present invention relates to a smart diffuser, such as a smart diffuser for sensing environmental information on the inside of a storage space such as a closet, emitting a diffusing agent, and transmitting the environmental information by means of near field communication, thereby continuously monitoring and managing the inside of the storage space.

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

Abstract: A semiconductor device connected by an anisotropic conductive film. The anisotropic conductive film includes a composition for an anisotropic conductive film including a first epoxy resin having an exothermic peak temperature of about 80° C. to about 110° C. and a second epoxy resin having an exothermic peak temperature of 120° C. to 200° C., as measured by differential scanning calorimetry (DSC). The first epoxy resin and the second epoxy resin are present in combined amount of about 30 wt % to about 50 wt % based on a total weight of the composition in terms of solid content. The second epoxy resin is present in an amount of about 60 to about 90 parts by weight based on 100 parts by weight of the first and second epoxy resins.

Abstract: A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

Abstract: The present invention relates to compositions and methods for treating fatty liver, steatohepatitis, or liver cirrhosis as well as insulin resistance and aging by administration of a DLK1-Fc fusion protein constructed by conjugation of an extracellular domain of DLK1 or a fragment thereof with a human antibody Fc region. Also provided are health functional foods containing a DLK1-Fc fusion protein constructed by conjugation of an extracellular domain of DLK1 (delta-like 1 homolog) or a fragment thereof with a human antibody Fc region as an active ingredient.

Abstract: There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

Abstract: Disclosed are a human antibody comprising a human complementarity-determining region (CDR), which binds specifically to c-Met, and a framework region (FR), a polynucleotide encoding the human antibody, an expression vector comprising the polynucleotide, a transformant transformed with the expression vector, a method of producing the human antibody B7 by culturing the transformant, a wound healing composition comprising the human antibody as an active ingredient, a cell regeneration composition comprising the antibody as an active ingredient, and a drug conjugate comprising a drug linked to the human antibody. The c-Met-specific human antibody can function as an HGF mimic that can be used as a wound healing composition. The antibody can be widely used to determine the treatment and prognosis of various diseases, including neuronal infarction, progressive nephropathy, liver cirrhosis, lung fibrosis, kidney injury, liver injury, lung injury, and ulcerative wounds, which are treated by activation of HGF or c-Met.

Abstract: The present invention is directed to a photographing lens containing, in order from an object side: a first lens having a positive refractive power and a convex surface facing the object side; a second lens having a negative refractive power; a third lens having a positive refractive power; and a fourth lens having a negative refractive power and at least one aspheric surface, the photographing lens satisfying the following conditional expressions: L T f ? 1.2 0.5 ? f 3 f ? 1.0 where LT denotes the distance on the optical axis between the object side of the first lens and the image side of the fourth lens; f denotes the total focal length of the photographing lens; and f3 denotes the focal length of the third lens.