Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

Abstract: The present invention relates to a TNF-? (tumor necrosis factor-alpha)/CXCL-10 (C-X-C motif chemokine 10) double targeting antibody based on the IgG format. Specifically, it was verified that an antibody, in which scFv having a heavy chain variable domain and a light chain variable domain of the CXCL10 specific antibody links to the C-terminus of the heavy chain constant domain of the TNF-? specific antibody, is a bispecific antibody that effectively binds to both TNF-? and CXCL10, and thus the antibody can be useful as a double targeting antibody capable of identifying TNF-?/CXCL10. A composition of the present invention comprises a TNF-?/CXCL-10 double targeting antibody which effectively binds to both TNF-? and CXCL10. The double targeting antibody of the present invention has excellent TNF-? inhibitory activity and osteoclast differentiation inhibitory activity compared with the TNF-? or CXCL10 single targeting antibody.

Abstract: Provided is a navigation system, which is effectively used depending on driver characteristics and driving conditions, wherein display performance of DUCs including a cluster, front/rear AVNs, and operation systems thereof are controlled through a single controller.

Abstract: An organic light emitting diode display includes a substrate, a semiconductor disposed on the substrate that includes a channel for each of a plurality of transistors and doping regions formed at both sides of each channel; a gate insulating layer disposed on the semiconductor that includes an insulating layer opening through which the doping regions of two different transistors are exposed; a gate electrode disposed on the gate insulating layer that overlaps each channel; an interlayer insulating layer disposed on the gate electrode that includes a first and second contact holes through which the doping regions exposed within the insulating layer opening are each exposed; and data wirings disposed on the interlayer insulating layer that are each connected to the doping regions. The interlayer insulating layer includes an organic layer, and the first and second contact holes each include a first side wall positioned within the insulating layer opening.

Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

Abstract: Provided are an optical lens assembly and an electronic apparatus including the same. The optical lens assembly implements a wide-angle lens system by including a first lens group having positive refractive power, an iris diaphragm, and a second lens group having positive refractive power, where the first lens group, the iris diaphragm, and the second lens group are arranged from an object side to an image side, and the first lens group includes at least one negative lens and two positive lenses.

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: Systems and methods for automated voxel positioning in magnetic resonance spectroscopy (“MRS”) are provided. In some aspects, a method includes receiving magnetic resonance (“MR”) imaging data acquired from a subject using an MR imaging system and registering the MR imaging data to an atlas having a pre-defined volume of interest (“VOI”), or segmenting a region of interest (“ROI”) directly from the MR data. The method also includes generating registration parameters based on the registration, and computing a transformed VOI using the pre-defined VOI in the atlas and the registration parameters. Alternatively, the VOI may be obtained by directly estimating it from the ROI.

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Abstract: A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the ceil region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

Abstract: A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region.

Abstract: A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.