Patents by Inventor Yu-Hua Chen

Yu-Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141224
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 27, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
  • Publication number: 20180323143
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 8, 2018
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 10083901
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: September 25, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Cheng-Ta Ko
  • Patent number: 10068847
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 4, 2018
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 9970519
    Abstract: A circulation member positioning structure for a ball screw includes a nut and a circulation member. The nut has a threaded channel, a socket, and a positioning notch. The socket is provided on a wall of the threaded channel and the positioning notch is provided on a wall of socket. The circulation member has a circulation portion, a circulation track, and a positioning protrusion. The circulation portion is provided in the socket of the nut. The circulation track is distributed over one lateral of the circulation portion and connects with the threaded channel of the nut. The positioning protrusion is provided on an opposite lateral of the circulation portion for being engaged with the positioning notch of the nut. Thereby, the circulation member positioning structure helps to simplify the assembling work of the circulation member and to remain the nut small despite the insertion of the circulation member.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 15, 2018
    Assignee: HIWIN TECHNOLOGIES CORP.
    Inventors: Ming-Yao Lin, Yu-Hua Chen, Hui-Chen Chen, Tsung-Hsien Tsai
  • Publication number: 20180122733
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Application
    Filed: December 25, 2017
    Publication date: May 3, 2018
    Inventors: Yu-Hua CHEN, Cheng-Ta KO
  • Publication number: 20180096889
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Applicant: Unimicron Technology Corp.
    Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
  • Publication number: 20180070452
    Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Applicant: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Shih-Lian Cheng, Yu-Hua Chen, Cheng-Ta Ko, Jui-Jung Chien, Wei-Tse Ho
  • Patent number: 9887153
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 6, 2018
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yu-Hua Chen, Cheng-Ta Ko
  • Publication number: 20180014404
    Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 11, 2018
    Inventors: Yu-Chung HSIEH, Chun-Hsien CHIEN, Wei-Ti LIN, Yu-Hua CHEN
  • Publication number: 20180005931
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Application
    Filed: September 6, 2016
    Publication date: January 4, 2018
    Inventors: Yu-Hua CHEN, Cheng-Ta KO
  • Patent number: 9859159
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 2, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
  • Patent number: 9860980
    Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: January 2, 2018
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yu-Chung Hsieh, Chun-Hsien Chien, Wei-Ti Lin, Yu-Hua Chen
  • Patent number: 9854671
    Abstract: A circuit board includes a substrate, a first magnetic structure, a first dielectric layer and an inductive coil. The substrate has a top surface and a bottom surface. The first magnetic structure is disposed on the top surface of the substrate. The first dielectric layer covers the substrate and the first magnetic structure. The inductive coil includes a first interconnect, a second interconnect and a plurality of conductive pillars. The first interconnect is disposed on the first dielectric layer. The second interconnect is disposed on the bottom surface of the substrate. The conductive pillars connect the first interconnect and the second interconnect. The first interconnect, the second interconnect and the conductive pillars form a helical structure surrounding the first magnetic structure.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: December 26, 2017
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Yu-Chung Hsieh, Yu-Hua Chen
  • Patent number: 9737607
    Abstract: A polymer and a pharmaceutical composition employing the same are disclosed. The polymer includes a first repeating unit, a second repeating unit, and a third repeating unit. In particular, the first repeating unit is the second repeating unit is wherein R1 is C1-6 alkyl group; and the third repeating unit is wherein X is and Y is a hydrophilic polymeric moiety.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: August 22, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jui-Hsiang Chen, Yu-Hua Chen, Chia-Chen Tsai, Tse-Min Teng, Ting-Yu Shih, Chia-Chun Wang, Chia-wei Hong, Jennline Sheu, Hui-Ling Cheng, Shu-Feng Chen, Hung-Jui Huang, Shu-Ling Wang
  • Publication number: 20170194249
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 9601474
    Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: March 21, 2017
    Assignee: Invensas Corporation
    Inventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Patent number: 9578742
    Abstract: A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 21, 2017
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Shih-Liang Cheng, Dyi-Chung Hu, Yu-Hua Chen
  • Publication number: 20170048973
    Abstract: A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 16, 2017
    Inventors: Shih-Liang CHENG, Dyi-Chung HU, Yu-Hua CHEN
  • Publication number: 20170025342
    Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.
    Type: Application
    Filed: October 6, 2016
    Publication date: January 26, 2017
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Yu-Hua Chen, Ra-Min Tain