Patents by Inventor Yu Min Lin

Yu Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11062197
    Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 13, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 11061305
    Abstract: A light path adjustment mechanism includes a support, a carrier, an optical plate member and a raised structure. The carrier is disposed in the support and connected to the support by a first connection bar and a second connection bar. The optical plate member is disposed on the carrier, and the raised structure is provided on a periphery of the carrier and integrally formed as one piece with the carrier.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 13, 2021
    Assignee: YOUNG OPTICS INC.
    Inventors: Yu-Chen Chang, Han-Min Chiu, Wei-Szu Lin, Sheng-Ya Hsu
  • Patent number: 11063157
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 11004816
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Publication number: 20210118860
    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
    Type: Application
    Filed: May 27, 2020
    Publication date: April 22, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
  • Publication number: 20210111126
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
  • Publication number: 20210111153
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
  • Publication number: 20210111125
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.
    Type: Application
    Filed: August 27, 2020
    Publication date: April 15, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
  • Publication number: 20210082810
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 18, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Patent number: 10921063
    Abstract: A heat dissipation unit includes a main body and a mesh body. The main body has an upper plate and a lower plate. The upper and lower plates are correspondingly overlapped and mated with each other to together define an airtight chamber. A working fluid is contained in the airtight chamber. One face of the lower plate, which faces the airtight chamber, is formed with a capillary structure by means of laser processing. The mesh body is attached to the face of the lower plate with the capillary structure. By means of the mesh body, the liquid working fluid backflow efficiency of the capillary structure can be enhanced and the water content of the internal evaporation section of the heat dissipation unit can be increased to avoid dry burn.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 16, 2021
    Assignee: Asia Vital Components Co., Ltd.
    Inventor: Yu-Min Lin
  • Publication number: 20210035914
    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 4, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Han Lin, Yu-Min Lin, Tao-Chih Chang
  • Publication number: 20210013256
    Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
    Type: Application
    Filed: September 11, 2020
    Publication date: January 14, 2021
    Inventors: Yu-Min LIN, Tao-Chih CHANG
  • Publication number: 20200328827
    Abstract: An antenna control method comprises obtaining a plurality of radio frequency signal parameters respectively in a plurality of measuring beam directions, generating a plurality of parameter groups according to the plurality of radio frequency signal parameters, selecting a target beam direction from the plurality of measuring beam directions according to the plurality of parameter groups, and controlling an antenna to transmit and receive signals in the target beam direction. In said antenna control method, two adjacencies of the plurality of measuring beam directions have an angle difference therebetween, and each of the plurality of parameter groups comprises more than one of the plurality of radio frequency signal parameters.
    Type: Application
    Filed: October 16, 2019
    Publication date: October 15, 2020
    Inventors: YU-MIN LIN, CHIEN SHENG CHEN
  • Patent number: 10784297
    Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 22, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Min Lin, Tao-Chih Chang
  • Publication number: 20200151970
    Abstract: A method for tire force reserve estimation is applicable to a vehicle. In the method, vehicle motion information including the longitudinal acceleration, the lateral acceleration, the change of the tire rotation angle at different times, the change of the yaw at different times, the steering angle of the steering tires, etc. is continuously detected, for estimating the current normal force, the current longitudinal force and the current lateral force of each of the tires. Finally, the current normal force, the current longitudinal force, the current lateral force and the coefficient of friction of the road relative to the tires are applied to estimate the longitudinal tire force reserve and the lateral tire force reserve.
    Type: Application
    Filed: December 7, 2018
    Publication date: May 14, 2020
    Inventors: Bo-Chiuan Chen, Ya-Yu You, Yu-Min Lin, Wei-Jie Chen, Yuan-Chun Chen, Di Ku
  • Patent number: 10608088
    Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 31, 2020
    Assignee: AU OPTRONICS CORP.
    Inventors: Yu-Min Lin, Kuo-Lung Fang, Feng-Yuan Gan
  • Publication number: 20200088472
    Abstract: A heat dissipation unit includes a main body and a mesh body. The main body has an upper plate and a lower plate. The upper and lower plates are correspondingly overlapped and mated with each other to together define an airtight chamber. A working fluid is contained in the airtight chamber. One face of the lower plate, which faces the airtight chamber, is formed with a capillary structure by means of laser processing. The mesh body is attached to the face of the lower plate with the capillary structure. By means of the mesh body, the liquid working fluid backflow efficiency of the capillary structure can be enhanced and the water content of the internal evaporation section of the heat dissipation unit can be increased to avoid dry burn.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventor: Yu-Min Lin
  • Publication number: 20200075519
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Patent number: 10526369
    Abstract: The present invention provides a cell penetrating peptide dimer by oxidative modification, in which each monomer is connected with each other by the disulfide linkage. The drugability of the peptide dimer has been improved through enhancing stability, reducing proteolysis, retaining permeability and increasing heparan sulfate binding specificity. The modified peptide products can be used to deliver drug molecules as a suitable drug carrier for targeted therapy.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: January 7, 2020
    Inventors: Yu-Min Lin, Wei-Chen Chen, Win-Chin Chiang, Ting Lian Chang, Chun-Hung Kuo
  • Patent number: D898268
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 6, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Tsung-Huan Tsai, Yu-Min Lin, Chin-Hao Chi, Wei-Yuan Tsou