Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.

Abstract: An interspinous spacer that includes a body having a distal portion and a proximal portion; an actuator at least partially disposed in the body; and a first arm and a second arm, where the first and second arms are rotatably coupled to a distal portion of the body and coupled to the actuator, where the actuator, first arm, and second arm are configured, upon rotation of the actuator in a first direction, to move the first and second arms from an implantation position, in which the first and second arms extend from the distal portion of the body back toward the proximal portion of the body, to a deployed position, in which the first and second arms extend away from the body.

Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.

Abstract: An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

Abstract: The application provides a content addressable memory (CAM) memory device and a method for searching and comparing data thereof. The CAM memory device comprises: a plurality of CAM memory strings; and a sensing amplifier circuit coupled to the CAM memory strings; wherein in data searching, a search data is compared with a storage data stored in the CAM memory strings, the CAM memory strings generate a plurality of memory string currents, the sensing amplifier circuit senses the memory string currents to generate a plurality of sensing results: based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.

Abstract: An optical sensor module and a packaging method thereof are disclosed, wherein the optical sensor module comprises a substrate having a light sensing element; and a housing made of a transparent material. The housing is connected to the substrate and covers the light sensing element. The housing has a light-receiving area facing the light sensing element, and the inner surface of the housing toward the substrate is provided with a light-shielding coating in a portion outside of the light-receiving area. In this way, optical components such as the light sensor can be effectively protected, and still retain the effect of avoiding noise light interference with the light sensor module.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A power detection circuit is provided for detecting current total input power of a resonant circuit. The power detection circuit includes a detection circuit and an estimation circuit. The detection circuit receives a current signal and obtains resonant-slot baseband power according to the current signal to generate the baseband power value. The current signal represents a resonant-slot current generated by the resonant circuit. The estimation circuit receives the baseband power value and estimates the current total input power according to the baseband power value to generate an estimated power value.

Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent impedance. The detection unit detects the resonant tank current and the resonant tank voltage to acquire associated parameters. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates an impedance value of the resonant tank equivalent impedance according to the inductance of the resonant tank equivalent inductor, a time difference, the resonant period, a reference current value, a negative peak current value and a second expression.

Abstract: The invention provides an optical measurement device for measuring light to be inspected. The optical measurement device comprises a light receiving module, a light splitting module, and a plurality of color filters. The light receiving module is used for converting the light to be inspected into a first parallel light. The light splitting module is used for splitting the first parallel light into a plurality of parallel lights to be inspected. Each color filter receives at least one of the plurality of parallel lights to be inspected. The plurality of parallel lights to be inspected filtered by the plurality of color filters are used to calculate tristimulus values in the CIE color space.

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

Abstract: Disclosed are TCAM device and operation method thereof. The operation method of the TCAM device comprises: applying a select voltage on one of a plurality of first signal lines, and applying an pass voltage on the rest of the first signal lines, wherein the TCAM device comprises an IMS array, the IMS array comprises a plurality of memory units, the memory units are arranged as a plurality of rows and a plurality of columns, a plurality of control terminal of each row of the memory units are coupled to the first driving circuit via a first signal line, each column of the memory units are serially connected to form a memory unit string, each of the memory unit string is coupled to the second driving circuit via a second signal line; and applying a plurality of searching voltage corresponding to a target data to the second signal lines.

Abstract: A radio frequency circuit with font routing to replace a resistor includes a routing layer and a ground layer. The routing layer includes a first pad, a second pad and a font routing unit. The second pad is corresponding to the first pad. The font routing unit is connected between the first pad and the second pad, and has a trace width. The trace width is less than a 50 ohm trace width. The ground layer is disposed below the routing layer and is separated from the routing layer by a height. The font routing unit has a second equivalent impedance at the radio frequency, the second equivalent impedance is determined according to the trace width, the height and the radio frequency, and the second equivalent impedance is the same or similar to a first equivalent impedance.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Abstract: A computing device determines an optimal number of threads for a computer task. Execution of a computing task is controlled in a computing environment based on each task configuration included in a plurality of task configurations to determine an execution runtime value for each task configuration. An optimal number of threads value is determined for each set of task configurations having common values for a task parameter value, a dataset indicator, and a hardware indicator. The optimal number of threads value is an extremum value of an execution parameter value as a function of a number of threads value. A dataset parameter value is determined for a dataset. A hardware parameter value is determined as a characteristic of each distinct executing computing device in the computing environment. The optimal number of threads value for each set of task configurations is stored in a performance dataset in association with the common values.

Abstract: The present invention relates to a method for quantitative measurement of catechol estrogen bound protein in blood sample. By detecting adduction levels of binding sites of the catechol estrogen on the protein in blood sample, the catechol estrogen bound protein in the blood sample can be detected quantitatively and a limit of quantitation can be decreased.