Abstract: An antenna control method comprises obtaining a plurality of radio frequency signal parameters respectively in a plurality of measuring beam directions, generating a plurality of parameter groups according to the plurality of radio frequency signal parameters, selecting a target beam direction from the plurality of measuring beam directions according to the plurality of parameter groups, and controlling an antenna to transmit and receive signals in the target beam direction. In said antenna control method, two adjacencies of the plurality of measuring beam directions have an angle difference therebetween, and each of the plurality of parameter groups comprises more than one of the plurality of radio frequency signal parameters.

Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

Abstract: A heat dissipation unit includes a main body and a mesh body. The main body has an upper plate and a lower plate. The upper and lower plates are correspondingly overlapped and mated with each other to together define an airtight chamber. A working fluid is contained in the airtight chamber. One face of the lower plate, which faces the airtight chamber, is formed with a capillary structure by means of laser processing. The mesh body is attached to the face of the lower plate with the capillary structure. By means of the mesh body, the liquid working fluid backflow efficiency of the capillary structure can be enhanced and the water content of the internal evaporation section of the heat dissipation unit can be increased to avoid dry burn.

Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

Abstract: An antenna control method comprises obtaining a plurality of radio frequency signal parameters respectively in a plurality of measuring beam directions, generating a plurality of parameter groups according to the plurality of radio frequency signal parameters, selecting a target beam direction from the plurality of measuring beam directions according to the plurality of parameter groups, and controlling an antenna to transmit and receive signals in the target beam direction. In said antenna control method, two adjacencies of the plurality of measuring beam directions have an angle difference therebetween, and each of the plurality of parameter groups comprises more than one of the plurality of radio frequency signal parameters.

Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

Abstract: A method for tire force reserve estimation is applicable to a vehicle. In the method, vehicle motion information including the longitudinal acceleration, the lateral acceleration, the change of the tire rotation angle at different times, the change of the yaw at different times, the steering angle of the steering tires, etc. is continuously detected, for estimating the current normal force, the current longitudinal force and the current lateral force of each of the tires. Finally, the current normal force, the current longitudinal force, the current lateral force and the coefficient of friction of the road relative to the tires are applied to estimate the longitudinal tire force reserve and the lateral tire force reserve.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: A heat dissipation unit includes a main body and a mesh body. The main body has an upper plate and a lower plate. The upper and lower plates are correspondingly overlapped and mated with each other to together define an airtight chamber. A working fluid is contained in the airtight chamber. One face of the lower plate, which faces the airtight chamber, is formed with a capillary structure by means of laser processing. The mesh body is attached to the face of the lower plate with the capillary structure. By means of the mesh body, the liquid working fluid backflow efficiency of the capillary structure can be enhanced and the water content of the internal evaporation section of the heat dissipation unit can be increased to avoid dry burn.

Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Abstract: The present invention provides a cell penetrating peptide dimer by oxidative modification, in which each monomer is connected with each other by the disulfide linkage. The drugability of the peptide dimer has been improved through enhancing stability, reducing proteolysis, retaining permeability and increasing heparan sulfate binding specificity. The modified peptide products can be used to deliver drug molecules as a suitable drug carrier for targeted therapy.

Abstract: A piezoelectric motorization system for driving mechanical loads multi-dimensionally by an electronic circuitry is disclosed. The piezoelectric motorization system has a piezoelectric apparatus that is constructed by a mechanically flexible body that has multiple piezoelectric actuators attached its surfaces, where these actuators are controlled by an electronic circuitry. The mechanically flexible body has a finite structure with a sets of boundary conditions to determine its out-of-plane resonant modes. The electronic circuitry inject at least two sets of control signals into different groups of actuators at or near different resonant frequencies. Using these control signals, traveling waves can be generated on the piezoelectric apparatus to move mechanical loads placed on its surface. Or, the traveling waves are used to propel the piezoelectric apparatus for motorization.

Abstract: A chip package module includes an encapsulation layer, a chip, a substrate and a plurality of blind-hole electrodes. The encapsulation layer includes a first surface and a second surface opposite to the first surface. The chip includes a third surface and a fourth surface opposite to the third surface. A metal bump is fabricated on the third surface of the chip. The chip is embedded into the encapsulation layer from the first surface of the encapsulation layer. The metal bump is exposed from the first surface of the encapsulation layer. The substrate includes a metal layer, wherein the metal layer of the substrate is bonded to the chip through the metal bump. The plurality of blind-hole electrodes pass through the second surface of the encapsulation layer and are electrically connected to the metal layer of the substrate.