Patents by Inventor Yu Pan

Yu Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11938567
    Abstract: A laser fusion welding device includes a 1.9 ?m laser light source, a control unit and a light spot adjusting device. The control unit is configured to control the laser light source and the light spot adjusting device to adjust a laser power density at an object to be subjected to fusion welding. The 1.9 ?m laser light source has output power of 100-500 W. The control unit includes a time control unit, a power control unit and a light spot control unit. The time control unit is configured to control a turn-on time of the laser light source. The power control unit is configured to control the output power of the laser light source. The light spot control unit is configured to control the light spot adjusting device to adjust a size of a light spot at the object to be subjected to fusion welding.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: March 26, 2024
    Assignee: XINJIANG TECHNICAL INSTITUTE OF PHYSICS AND CHEMISTRY, CHINESE ACADEMY OF SCIENCES
    Inventors: Linjun Li, Shilie Pan, Xiaoming Duan, Yu Zhou, Yingjie Shen, Qianqian Hao, Yuqiang Yang, Xin He
  • Publication number: 20240098544
    Abstract: Systems and methods for indicating positioning information in wireless communication systems are disclosed. In one aspect, a method includes receiving, by a wireless communication device from a network, network timing error information; and reporting, by the wireless communication device to the network, downlink measurement results and User Equipment (UE) timing error information, wherein, the network timing error information comprises at least one of Transmission and Reception Point (TRP) transmission Timing Error Group (TEG) information and TRP reception TEG information; the UE timing error information comprises at least one of UE transmission TEG information and UE reception TEG information.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 21, 2024
    Applicant: ZTE CORPORATION
    Inventors: Yu PAN, Guozeng ZHENG, Chuangxin JIANG, Shujuan ZHANG, Zhaohua LU
  • Patent number: 11937266
    Abstract: A method and apparatus are disclosed. In an example from the perspective of a first device, a grant is received from a network node. The grant allocates a set of sidelink data resources. One or more sidelink data transmissions are performed on the set of sidelink data resources. A second feedback information associated with the one or more sidelink data transmissions is received and/or detected. An uplink resource is derived. A first feedback information is transmitted on the uplink resource to the network node. The first feedback information is set based upon the second feedback information.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: March 19, 2024
    Assignee: ASUSTek Computer Inc.
    Inventors: Ming-Che Li, Li-Chih Tseng, Wei-Yu Chen, Li-Te Pan
  • Publication number: 20240083918
    Abstract: Disclosed are compounds of Formula (I), methods of using the compounds for inhibiting ALK2 activity and pharmaceutical compositions comprising such compounds. The compounds are useful in treating, preventing or ameliorating diseases or disorders associated with ALK2 activity such as cancer.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 14, 2024
    Inventors: Jun Pan, Yu Bai, Liangxing Wu, Wenqing Yao
  • Publication number: 20240071776
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU
  • Publication number: 20240071888
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
  • Publication number: 20240047436
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a first die disposed on and electrically coupled to a first redistribution structure and laterally covered by a first insulating encapsulation, a second die disposed over the first die and laterally covered by a second insulating encapsulation, a second redistribution structure interposed between and electrically coupled to the first and second dies, a third redistribution structure disposed on the second die and opposite to the second redistribution structure, and at least one thermal-dissipating feature embedded in a dielectric layer of the third redistribution structure and electrically isolated from a patterned conductive layer of the third redistribution structure through the dielectric layer. Through substrate vias of the first die are physically connected to the second redistribution structure or the first redistribution structure.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Hao-Yi Tsai, Kris Lipu Chuang, Hsin-Yu Pan
  • Patent number: 11894299
    Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR LTD
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Patent number: 11894341
    Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Publication number: 20240017151
    Abstract: A team sports vision training system based on extended reality, voice interaction and action recognition is configured to train vision and an action of a user. A head-mounted display device includes a task scenario player and a speech sensing module. An action capture device generates an action message. A computing server stores a scenario setting parameter group and includes a task scenario generating module, a speech recognition module and an action recognition module. The task scenario generating module generates a virtual task scenario image and a task parameter group according to the scenario setting parameter group. The speech recognition module generates a speech recognition result and a vision training result. Then action recognition module generates an action recognition result and a sport training result. The vision training result and the sport training result are configured to judge whether the user meets a training requirement.
    Type: Application
    Filed: May 11, 2023
    Publication date: January 18, 2024
    Inventors: Min-Chun HU, Hung-Kuo CHU, Pin-Xuan LIU, Tse-Yu PAN, Hsin-Shih LIN
  • Patent number: 11866704
    Abstract: A method of treating a subject suffering from cancer comprising a step of administering an effective amount of a group of double-stranded RNA molecules to the subject, wherein the RNA molecule is isolated or derived from a bacteria of the genus Escherichia. A method of inhibiting growth or proliferation of cancer cells comprising a step of contacting said cells with said RNA molecule; and a pharmaceutical composition for treating cancer comprising said RNA molecule and a pharmaceutically tolerable excipient. Also a double-stranded RNA molecule and a recombinant vector comprising the double-stranded RNA molecule.
    Type: Grant
    Filed: December 6, 2020
    Date of Patent: January 9, 2024
    Assignee: Macau University of Science and Technology
    Inventors: Zhi-Hong Jiang, Kai-Yue Cao, Yu Pan, Tong-Meng Yan
  • Publication number: 20240006180
    Abstract: Provided herein are methods of depositing tungsten (W) films without depositing a nucleation layer. In certain embodiments, the methods involve depositing a conformal layer of boron (B) on a substrate. The substrate generally includes a feature to be filled with tungsten with the boron layer conformal to the topography of the substrate including the feature. The reducing agent layer is then exposed to a continuous flow of hydrogen and pulses of fluorine-containing tungsten precursor in a pulsed CVD process. The conformal boron layer is converted to a conformal tungsten layer.
    Type: Application
    Filed: November 16, 2021
    Publication date: January 4, 2024
    Inventors: Yu PAN, Yao-Tsung HSIEH, Xiaolan BA, Juwen GAO
  • Patent number: 11845454
    Abstract: Embodiments for operational envelope detection (OED) with situational assessment are disclosed. Embodiments herein relate to an operational envelope detector that is configured to receive, as inputs, information related to sensors of the system and information related to operational design domain (ODD) requirements. The OED then compares the information related to sensors of the system to the information related to the ODD requirements, and identifies whether the system is operating within its ODD or whether a remedial action is appropriate to adjust the ODD requirements based on the current sensor information. Other embodiments are described and/or claimed.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: December 19, 2023
    Assignee: Motional AD LLC
    Inventors: You Hong Eng, James Guo Ming Fu, Scott D. Pendleton, Yu Pan
  • Publication number: 20230396308
    Abstract: A system and method for determining SFN using QCL information is disclosed. In one aspect, a method receiving, by a wireless communication device, a first set of quasi-co-location (QCL) information; receiving, by the wireless communication device, a transmission; and applying, by the wireless communication device, a second set of QCL information based on the first set of QCL information, wherein the second set of QCL information is different from the first set of QCL information.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 7, 2023
    Applicant: ZTE CORPORATION
    Inventors: Meng MEI, Chuangxin JIANG, Zhaohua LU, Shujuan ZHANG, Yu PAN
  • Publication number: 20230397082
    Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The disclosure provides a method performed by a first node in a wireless communication system is provided. The method includes transmitting, by the first node, a first message to a second node, the first message including first indication information, and transmitting, by the first node, a second message to a third node, the second message including second indication information, wherein the third node is a candidate node configured by network for the second node.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 7, 2023
    Inventors: Yu PAN, Fuyuan LI, Weiwei WANG, Lixiang XU, Hong WANG
  • Patent number: 11830866
    Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20230377640
    Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Publication number: 20230378151
    Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20230378152
    Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
  • Patent number: 11824054
    Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai