Patents by Inventor Yu Pan

Yu Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11745478
    Abstract: The present disclosure provides a transparent elastic composite film, which includes a first film layer; a thermoplastic polyurethane layer; and a second film layer; wherein the first film layer and the second film layer have a crosslinked network structure; the first film layer includes acrylic resin and aliphatic polyisocyanate, wherein the acrylic resin includes hydroxyl-containing acrylic resin, and a weight ratio of the acrylic resin to the aliphatic polyisocyanate is 1/1 to 1/1.2, and a weight ratio of the hydroxyl-containing acrylic resin to the acrylic resin is 0.1/1 to 0.18/1.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: September 5, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Chung Wu, Mei-Ru Lin, En-Yu Pan
  • Patent number: 11749640
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20230268260
    Abstract: A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kris Lipu Chuang, Tzu-Sung Huang, Chih-Wei Lin, Yu-fu Chen, Hsin-Yu Pan, Hao-Yi Tsai
  • Patent number: 11732014
    Abstract: The present invention relates to a transcription factor gene that plays a key role in Solanaceae fruit ripening. Plants overexpressing the gene have fruits with deeper pigmentation and ripen more rapidly than controls. The invention also relates to transgenic plants comprising said gene, and methods of making said plants.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: August 22, 2023
    Assignee: Syngenta Participations AG
    Inventors: Charles Baxter, Yu Pan, Thomas Charles Hodgman, Graham Barron Seymour, Rebecca Cade, Henricus Johannes Van Wijk, Glyn Bradley, Laurent Grivet, Laurie Boyden, Graham Ball, Paul Fraser
  • Patent number: 11735651
    Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
  • Publication number: 20230260866
    Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 17, 2023
    Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU
  • Publication number: 20230260944
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a stack of composite conductive structures disposed on the first redistribution structure, and an insulating encapsulation disposed on the first redistribution structure and laterally covering the semiconductor die and the stack of composite conductive structures. The stack of composite conductive structures includes a lower tier and an upper tier stacked upon the lower tier. Each of the lower tier and the upper tier includes a support layer, through material vias (TMVs) penetrating through the support layer, and a conductive adhesive member underlying the support layer and the TMVs.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: CHIH-TING LAI, Hsin-Yu Pan
  • Patent number: 11715519
    Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Chih Huang, Jui-Yu Pan, Kuo-Chyuan Tzeng
  • Publication number: 20230239888
    Abstract: Presented are systems and methods for parameter estimation. A wireless communication device may determine that a first number of PDCCH transmissions, scheduled from a wireless communication node, that are associated and are PDCCH candidates for blind detection decoding, is K, wherein K is an integer larger than 1. The wireless communication device may determine a second number of PDCCH candidates to be counted for monitoring. The wireless communication device may count the second number of PDCCH candidates for monitoring with respect to the first number of PDCCH transmissions.
    Type: Application
    Filed: February 8, 2023
    Publication date: July 27, 2023
    Inventors: Yu PAN, Chuangxin JIANG, Shujuan ZHANG, Zhaohua LU
  • Publication number: 20230239947
    Abstract: The present application relates to a method for adding a node in a mobile communication system. A method performed by a first node in a mobile communication system is provided. User equipment (UE) is connected to the first node and a second node. The method comprises: sending a message used for requesting or requiring an addition of a third node; and receiving an acknowledge message in response to the message.
    Type: Application
    Filed: January 24, 2023
    Publication date: July 27, 2023
    Inventors: Yu PAN, Lixiang XU, Hong WANG
  • Publication number: 20230239831
    Abstract: Techniques are described for performing timing-based positioning methods including measuring and/or reporting timing errors. An example technique includes, determining, by a communication node, measurement information that comprises a set of measurement results and a set of timing delays, wherein the set of measurement results include a first set of time values when positioning signals are sent or received by a processor of the communication node, and wherein the set of timing delays includes a second set of time values, each of the second set of time values is a difference between when a positioning signal is sent or received by the processor of the communication node and when the positioning signal is respectively transmitted or received by an antenna of the communication node; and transmitting, by the communication node, the set of measurement results and the set of timing delays to a second communication node.
    Type: Application
    Filed: April 4, 2023
    Publication date: July 27, 2023
    Applicant: ZTE Corporation
    Inventors: Yu PAN, Guozeng Zheng, Chuangxin Jiang, Zhaohua Lu
  • Patent number: 11705378
    Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Jiun-Yi Wu, Hsin-Yu Pan, Tsung-Ding Wang, Yu-Min Liang, Wei-Yu Chen
  • Patent number: 11705408
    Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
  • Publication number: 20230222682
    Abstract: A map optimizing method, applicable to an electronic device storing distance values and a map, includes: identifying, from the map, a first map point with a first estimated coordinate and a second map point with a second estimated coordinate generated based on a first marker and a second marker, respectively; generating, according to the first and second estimated coordinates, virtual cameras controlled by a virtual pose and with optical axes intersected at first and second intersection coordinates separated from each other by one of the distance values, in which the virtual cameras provide virtual frames indicating that the first and second markers are observed at the first and second intersection coordinates, respectively; and performing a global bundle adjustment to optimize the map, including adjusting the first and second estimated coordinates to reduce a sum of re-projection errors calculated according to real keyframes and the virtual frames.
    Type: Application
    Filed: August 16, 2022
    Publication date: July 13, 2023
    Inventors: Kuang-Yu PAN, WanLing YANG
  • Publication number: 20230223357
    Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 13, 2023
    Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
  • Publication number: 20230191755
    Abstract: The present disclosure provides a transparent elastic composite film, which includes a first film layer; a thermoplastic polyurethane layer; and a second film layer; wherein the first film layer and the second film layer have a crosslinked network structure; the first film layer includes acrylic resin and aliphatic polyisocyanate, wherein the acrylic resin includes hydroxyl-containing acrylic resin, and a weight ratio of the acrylic resin to the aliphatic polyisocyanate is 1/1 to 1/1.2, and a weight ratio of the hydroxyl-containing acrylic resin to the acrylic resin is 0.1/1 to 0.18/1.
    Type: Application
    Filed: September 19, 2022
    Publication date: June 22, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Chung WU, Mei-Ru LIN, En-Yu PAN
  • Publication number: 20230197667
    Abstract: A semiconductor device includes a substrate, an electronic component, a cover, a heat conduction component and a dam. The electronic component is disposed on the substrate. The cover is disposed on the substrate and covers the electronic component. The heat conduction component is disposed between the electronic component and the cover. The dam is disposed between the electronic component and the cover and surrounds the heat conduction component.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 22, 2023
    Inventors: Yu-Jin LI, Bo-Jiun YANG, Tai-Yu CHEN, Tsung-Yu PAN, Chun-Yin LIN
  • Publication number: 20230191482
    Abstract: The present invention provides a high-strength and high-plasticity titanium matrix composite and a preparation method thereof. The preparation method includes: preparing high-oxygen hydride-dehydride titanium powder using a high-temperature rotary ball grinding treatment process, in which the prepared hydride-dehydride titanium powder has a particle size of 10-40 ?m, and has an oxygen content of 0.8-1.5 wt. %; preparing high-purity ultra-fine oxygen adsorbent powder using a wet grinding method of high-energy vibration ball grinding treatment process; in which a purity of the oxygen adsorbent powder is ?99.9%, and a particle size of the oxygen adsorbent powder is ?8 ?m; mixing the high-oxygen hydride-dehydride titanium powder with the oxygen adsorbent powder in a protective atmosphere, and then press-forming the powder obtained after mixing to obtain a raw material blank; and performing atmosphere protective sintering treatment on the raw material blank to obtain a titanium matrix composite.
    Type: Application
    Filed: August 17, 2020
    Publication date: June 22, 2023
    Applicant: University of Science and Technology Beijing
    Inventors: Xin LU, Yu PAN, Yucheng YANG, Jiazhen ZHANG, Wei XU, Bowen LIU, Ce ZHANG, Jianzhuo SUN, Yanjun LIU, Xuanhui QU
  • Publication number: 20230192090
    Abstract: Among other things, techniques are described for determining precedence order at a multiway stop. In embodiments, identifications are assigned to tracks, and young tracks are compared to stale tracks. A young track matches a stale track based on one or more factors. An identification of the young track is reassigned to an identification of the stale track, wherein the young track is determined to match the stale track based on the one or more factors. An earliest time of appearance of agents is determined based on identifications and in view of perception obscured areas. A precedence order for navigating through the intersection is determined based on local rules, the identifications, and the earliest time of appearance of agents, and the vehicle proceeds through the multiway stop intersection in accordance with the precedence order.
    Type: Application
    Filed: January 25, 2022
    Publication date: June 22, 2023
    Inventors: Scott D. Pendleton, Xiaojun Sun, Shu-Kai Lin, Puneet Singhal, Yu Pan, Lubing Zhou, Laith Sahawneh, Guchan Ozbilgin, Giancarlo Baldan
  • Publication number: 20230171775
    Abstract: Provided are a transmission method and apparatus, a communication node, and a storage medium. The transmission method includes: determining control channel information and activated Transmission Configuration Indicator (TCI); determining a correspondence between the control channel information and the activated TCI; and receiving a control channel corresponding to the control channel information based on the correspondence and the activated TCI.
    Type: Application
    Filed: April 29, 2021
    Publication date: June 1, 2023
    Inventors: YU PAN, Chuangxin JIANG, Shujuan ZHANG, Zhaohua LU, Bo GAO, Zhen HE, Wenjun YAN