Abstract: A vapor-phase/liquid-phase fluid heat exchange unit includes: a first cover body having a first and a second side, a vapor outlet and a liquid inlet, the vapor outlet and the liquid inlet being in communication with the first and second sides; and a second cover body having a third and a fourth side, the first and second cover bodies being correspondingly mated with each other to together define a heat exchange space. A working fluid and a fluid separation unit are disposed in the heat exchange space. The fluid separation unit partitions the heat exchange space into an evaporation section corresponding to the vapor outlet and a backflow section corresponding to the liquid inlet.

Abstract: An interspinous spacer that includes a body having a distal portion and a proximal portion; an actuator at least partially disposed in the body; and a first arm and a second arm, where the first and second arms are rotatably coupled to a distal portion of the body and coupled to the actuator, where the actuator, first arm, and second arm are configured, upon rotation of the actuator in a first direction, to move the first and second arms from an implantation position, in which the first and second arms extend from the distal portion of the body back toward the proximal portion of the body, to a deployed position, in which the first and second arms extend away from the body.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

Abstract: A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.

Abstract: An optical sensor module and a packaging method thereof are disclosed, wherein the optical sensor module comprises a substrate having a light sensing element; and a housing made of a transparent material. The housing is connected to the substrate and covers the light sensing element. The housing has a light-receiving area facing the light sensing element, and the inner surface of the housing toward the substrate is provided with a light-shielding coating in a portion outside of the light-receiving area. In this way, optical components such as the light sensor can be effectively protected, and still retain the effect of avoiding noise light interference with the light sensor module.

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: The present invention provides an ambient light sensing method and an ambient light sensor. The ambient light sensing method comprises a light sensing device sensing the light passing through an optical filter and giving an optical signal value, and an operational unit receiving the optical signal value and calculating an ambient light illuminance value according to the optical signal value. Accordingly, the ambient light sensing method and the ambient light sensor according to the present invention can give the ambient light illuminance value with more accuracy and ensure low influence of opaque ink on ambient light sensing.

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

Abstract: A light sensor and a control method thereof are disclosed. The light sensor comprises a light-emitting element, a first light-sensing unit and a second light-sensing unit. The light-emitting element generates an emission signal. The light-sensitive characteristic of the first light-sensing unit corresponds to a first wavelength range. The light-sensitive characteristic of the second light-sensing unit corresponds to a second wavelength range, which is different from the first wavelength range. In this way, when the emission signal is reflected by an object and received by the first light-sensing unit and the second light-sensing unit, the type of the object may be determined based on the difference between the signal sensed by the first light-sensing unit and the signal sensed by the second light-sensing unit.

Abstract: A computing device selects new test configurations for testing software. Software under test is executed with first test configurations to generate a test result for each test configuration. Each test configuration includes a value for each test parameter where each test parameter is an input to the software under test. A predictive model is trained using each test configuration of the first test configurations in association with the test result generated for each test configuration based on an objective function value. The predictive model is executed with second test configurations to predict the test result for each test configuration of the second test configurations. Test configurations are selected from the second test configurations based on the predicted test results to define third test configurations. The software under test is executed with the defined third test configurations to generate the test result for each test configuration of the third test configurations.

Abstract: An interspinous spacer that includes a body having a distal portion and a proximal portion; an actuator at least partially disposed in the body; and a first arm and a second arm, where the first and second arms are rotatably coupled to a distal portion of the body and coupled to the actuator, where the actuator, first arm, and second arm are configured, upon rotation of the actuator in a first direction, to move the first and second arms from an implantation position, in which the first and second arms extend from the distal portion of the body back toward the proximal portion of the body, to a deployed position, in which the first and second arms extend away from the body.

Abstract: An optical sensor module and a packaging method thereof are disclosed, wherein the optical sensor module comprises a substrate having a light sensing element; and a housing made of a transparent material. The housing is connected to the substrate and covers the light sensing element. The housing has a light-receiving area facing the light sensing element, and the inner surface of the housing toward the substrate is provided with a light-shielding coating in a portion outside of the light-receiving area. In this way, optical components such as the light sensor can be effectively protected, and still retain the effect of avoiding noise light interference with the light sensor module.

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Abstract: A computing device determines an optimal number of threads for a computer task. Execution of a computing task is controlled in a computing environment based on each task configuration included in a plurality of task configurations to determine an execution runtime value for each task configuration. An optimal number of threads value is determined for each set of task configurations having common values for a task parameter value, a dataset indicator, and a hardware indicator. The optimal number of threads value is an extremum value of an execution parameter value as a function of a number of threads value. A dataset parameter value is determined for a dataset. A hardware parameter value is determined as a characteristic of each distinct executing computing device in the computing environment. The optimal number of threads value for each set of task configurations is stored in a performance dataset in association with the common values.

Abstract: The present invention relates to a method for quantitative measurement of catechol estrogen bound protein in blood sample. By detecting adduction levels of binding sites of the catechol estrogen on the protein in blood sample, the catechol estrogen bound protein in the blood sample can be detected quantitatively and a limit of quantitation can be decreased.