Patents by Inventor Yun Wang

Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11485239
    Abstract: Powerflow of a rechargeable energy storage system (RESS) is managed according to a method. The RESS has series-connected first and second battery elements with different characteristics. Each element, e.g., a pack, has a corresponding maximum or minimum voltage or current limit. Currents are predicted for each of the first and second battery elements via a controller using a corresponding voltage limit. A requested operating mode of the RESS is used to select a current for the elements. A voltage across the elements is predicted using the selected current and a corresponding battery state space model. The method predicts a total power capability of the RESS over a prediction horizon using the selected current to generate predicted power capability values. The requested operating mode is controlled over the horizon using the power capability values. A powertrain system includes the RESS, an inverter, an electric machine, and the controller.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 1, 2022
    Assignee: GM Global Technology Operations LLC
    Inventors: Yue-Yun Wang, Garrett M. Seeman, Jeffrey S. Piasecki
  • Patent number: 11489053
    Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220344215
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
  • Publication number: 20220344214
    Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first source/drain feature, a second source/drain feature and an interlayer dielectric (ILD) layer over the first and second source/drain features. The method also includes removing a portion of the ILD layer to form a cut feature opening and forming a hybrid cut feature therein to divide a to-be-formed metal layer into multiple pieces as source/drain contacts. The hybrid cut feature includes a conformal dielectric liner over the cut feature opening and a dielectric filler over the dielectric liner. During the formation of a source/drain contact opening, at least a portion of the dielectric liner extending along a sidewall of the dielectric filler is partially and selectively removed, leading to a dimension-reduced hybrid cut feature and thus a reduced spacing between two adjacent source/drain contacts.
    Type: Application
    Filed: September 2, 2021
    Publication date: October 27, 2022
    Inventors: Chung-Hao Cai, Chia-Hsien Yao, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220343372
    Abstract: A method for processing a video and a corresponding apparatus are provided. The method for processing the video includes determining a plurality of candidate commodities that will be recommended to a user, based on attribute information of the user and attribute information of a plurality of commodities to be promoted; sending recommendation information including the plurality of candidate commodities to a user terminal; receiving a selection instruction for a target commodity sent by the user terminal and a video created by the user for the target commodity, wherein the target commodity is selected by the user from the plurality of candidate commodities based on the recommendation information; and creating a promotional video by synthesizing sales information of the target commodity with the video.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 27, 2022
    Inventors: Yinhui LI, Jialu LIU, Yun WANG, Xinyi YIN
  • Publication number: 20220344353
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • Publication number: 20220336268
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Application
    Filed: May 2, 2022
    Publication date: October 20, 2022
    Inventors: Chao-Hsun WANG, Wang-Jung HSUEH, Kuo-YI CHAO, Mei-Yun WANG
  • Publication number: 20220336592
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Ting Fang, Chung-Hao Cai, Jui-Ping Lin, Chia-Hsien Yao, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220336367
    Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.
    Type: Application
    Filed: September 3, 2021
    Publication date: October 20, 2022
    Inventors: Chen-Hung Tsai, Chao-Hsun Wang, Pei-Hsuan Lee, Chih-Chien Chi, Ting-Kui Chang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220328622
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao CAI, Chun-Po CHANG, Chien-Yuan CHEN, Yen-Jun HUANG, Ting FANG, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20220328649
    Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220328639
    Abstract: A method for forming a FinFET device structure and method for forming the same is provided. The method includes forming an isolation structure over a substrate and forming a first dielectric layer over the isolation structure. The method includes forming a gate structure in the first dielectric layer and forming a deep trench through the first dielectric layer and the isolation structure. The method also includes forming an S/D trench in the first dielectric layer and filling a metal material in the deep trench and the S/D trench to form a deep contact structure and the S/D contact structure. A bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting FANG, Da-Wen LIN, Fu-Kai YANG, Chen-Ming LEE, Mei-Yun WANG
  • Publication number: 20220328304
    Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 13, 2022
    Inventors: Kuo-Chang Kau, Wen-Yun Wang, Chia-Chu Liu, Hua-Tai Lin
  • Patent number: 11467298
    Abstract: The present application provides a vector denoising method and a vector denoising device for multicomponent seismic data, which relate to the field of seismic data processing technologies. The vector denoising method for multicomponent seismic data includes: decomposing multicomponent seismic gather data to obtain a plurality of small multicomponent seismic data; obtaining quaternary frequency domain seismic data by performing a quaternary Fourier transformation according to each of the plurality of small multicomponent seismic data; extracting frequency slices from the quaternary frequency domain seismic data in a quaternary frequency domain, and filtering the frequency slices by using a Cadzow filtering method to obtain filtered quaternary frequency domain seismic data; and performing an inverse quaternary Fourier transformation on the filtered quaternary frequency domain seismic data to obtain filtered seismic data of each component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 11, 2022
    Assignee: INSTITUTE OF GEOCHEMISTRY, CHINESE ACADEMY OF SCIENCES
    Inventors: Chao Wang, Yun Wang
  • Publication number: 20220309627
    Abstract: A face image straight line processing method, a terminal device, and a storage medium are provided. The method includes: detecting faces and straight lines in an image; determining attributes of each of straight lines based on positions of face frames, and start coordinates and end coordinates of the straight lines; extracting an effective line set from the straight lines; and keeping, during performing face distortion correction on the image, relative positions of points on effective lines in the effective line set unchanged.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 29, 2022
    Inventor: Yun WANG
  • Publication number: 20220309248
    Abstract: A method and system for product knowledge fusion are discloses. The method includes following steps: acquiring original data of a product; performing knowledge extraction on the original data of the product to obtain entities, attributes and semantic relationships related to the product; building an entity information knowledge base according to the entities, attributes and semantic relationships related to the products; fusing the semantic relationships and attributes with the entities and matching the entities by adopting a text matching model to obtain original data of the product corresponding to matched entity information; and establishing a knowledge graph of the product according to the matched entity information. The method and system standardize multi-source heterogeneous data with a knowledge fusion method, thus effectively reducing polysemy and unclear references of knowledge caused by different data structures and sources.
    Type: Application
    Filed: February 23, 2022
    Publication date: September 29, 2022
    Applicant: China Academy of Art
    Inventors: Zheng LIU, Xin WANG, Ming SHAO, Ke ZONG, Yun WANG
  • Publication number: 20220310455
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220310398
    Abstract: A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 29, 2022
    Inventors: Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11454435
    Abstract: An accumulator, including a housing and a cover body, one end of the housing being open; the housing is internally provided with an accommodating cavity, the accommodating cavity being internally provided with a filter; a peripheral wall of the housing comprises a first thick wall part, the first thick wall part being provided with an inlet channel, and one end of the inlet channel communicating with the accommodating cavity, while the other end of the inlet channel communicates with the outside; one end of an outlet channel communicates with the accommodating cavity by means of the filter, while the other end of the outlet channel communicates with an outer portion of the housing. The accumulator may be directly welded and fixed to a heat exchange core without requiring a pipeline connection, the risk of external leakage being small, and the anti-seismic performance being high.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 27, 2022
    Assignee: Zhejiang Sanhua Intelligent Controls Co., Ltd.
    Inventors: Bing Zhang, Yun Wang, Ran Ding, Rongrong Zhang
  • Publication number: 20220301121
    Abstract: The present disclosure provides a method for correcting face distortion, an apparatus for correcting face distortion, an electronic device, and a storage medium. The method includes: performing face detection on an obtained image to determine a position of each face box included in the image; determining whether each face box is within a predetermined field of view range based on the position of the face box; and performing distortion correction on a face in a first face box in response to at least a part of the first face box being not within the predetermined field of view range, to generate a corrected image.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventor: Yun Wang