Abstract: A portable electronic device and control method thereof perform an unlocking operation and several page turning operations for a display of the portable electronic device. Light intensities in several positions of the light sensors are detected in a preset time period. The portable electronic device determines whether the operating mode is a predetermined operating mode and determines whether the portable electronic device is locked by the detected light intensities. The portable electronic device unlocks the portable electronic device upon detecting the portable electronic device is locked. Furthermore, the portable electronic executes at least one page turning operation on the display unit upon detecting the portable electronic device is unlocked.

Abstract: Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.

Abstract: A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights.

Abstract: A handlebar grip comprises a sleeve, a clamping device and a fastening means. The sleeve made of rigid plastic materials includes a cylindrical body, a front opening end, a rear opening end and at least a vacant area near the rear opening end. The clamping device includes a ring-shaped body, a first extending end and a second extending end. A slot is defined by the first and second extending ends. The clamping device further has at least a protruding disposed on the inner surface of the body. The clamping device is fitted around the rear opening end of the sleeve in such a way that the protruding of the clamping device is wedged into the vacant area of the sleeve. The fastening means includes a threaded bore and a screw. The bore extends through the first and second extending ends of the clamping device along a reference axis. The screw has a shaft with a proximal end and a distal end opposite the proximal end, a head disposed on the proximal end and a threaded region.

Abstract: In one embodiment a first comparison result is determined based on a link quality metric and a first threshold value.

Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Abstract: The present invention is related to a composition and method of adipose cell differentiation inhibition.

Abstract: A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

Abstract: A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.

Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.

Abstract: A mood-interacting shoe device includes a shoe body and an interactive sensing mechanism. The interactive sensing mechanism further includes a heart rate sensor, a speed sensor, a pressure sensor, a microprocessor and a radio frequency emitter. The heart rate sensor senses the heart rate value, the speed sensor senses the marching rate, and the pressure sensor senses the pressure distribution value when the thenar exerts pressure. The sensed values will be transmitted to the microprocessor, where the sensed values are analyzed and thereby the mood of the user is determined accordingly. The analysis result is transmitted to the video and music player through the radio frequency emitter, such that the video and music player can play music corresponding to the mood; and a LED display unit is further provided such that the user can understand whether each sensor operates normally or not.

Abstract: Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface.

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Abstract: A group keypad structure in compliance with a standard keyboard installation includes group keypads corresponding to characters of a standard keyboard input method; for example, the structure includes ten group keypads installed from left to right on a base, and the ten group keypads include characters of “Q, A, Z”, “W, S, X”, “E, D, C”, “R, F, V”, “T, G, B”, “Y, H, N”, “U, J, M”, “I, K, ,”, “O, L, .” and “P, ;, /” respectively, and further includes ten numeric characters “1˜0”, so as to achieve the effects of reducing the area of a keyboard, shortening the moving distance of a user's fingers, providing an easy and convenient carry, complying with the user's using habit, and improving the input speed.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.