Abstract: The present invention provides a method of fabricating semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x<y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.

Abstract: Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti) and tungsten nitride (WN); at least one second layer over the first layer, the at least one second layer selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), ruthenium (Ru), rhodium (Rh), platinum (Pt) and cobalt (Co); a seed layer for copper (Cu); and copper (Cu) filling a remaining portion of the opening.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Abstract: A liquid cooling module has a sealed unit and a heat dissipating module connected by multiple flexible pipes. The sealed unit has a contacting surface attached to an electronic element. The heat dissipating module has a radiator, coolant tanks and a pump all mounted compactly together. The radiator has multiple fins and tubes to allow the coolant to flow through and dissipate heat and may have a fan to increase airflow. The coolant tank is formed on the radiator. The pump circulates the coolant along the coolant pipes. Accordingly, the liquid cooling module has a compact structure and the coolant pipes are flexible, so the liquid cooling module can be mounted simply in a computer case, and is installed easily by home users and professionals alike.

Abstract: A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.

Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

Abstract: An integrated heat dissipating assembly includes two heat sinks, a heat dissipating fan mounted between the two sinks and a body provided below the two heat sinks and the heat dissipating fan. The body is composed of a hollow body, a pump received inside the hollow body and a base attached to a bottom face of the hollow body for conducting heat from a heat source. The hollow body is divided into receiving spaces respectively communicating with water channels of the two heat sinks such that cooling water flowing inside the hollow body and the water channels of the two heat sinks is able to take away heat from the base. The heat is then dissipated by cool air due to the heat dissipating fan.

Abstract: The present invention provides a DC to DC conversion circuit, comprising a DC power supply, a DC to DC converter, a power management IC and a load, wherein the load may be a backlight source of a liquid crystal display. The power management IC controls the DC to DC converter to convert a DC voltage supplied by the DC power supply to an output voltage of the DC to DC converter, which is supplied to the load. The power management IC is capable of controlling the DC to DC converter to adjust the output voltage to a minimum voltage actually needed by the load according to the variation of the minimum voltage which is actually needed by the load.

Abstract: A balance-enhancing and vibration-reducing device is incorporated in a wrist exerciser to enhance force balance and reduce vibration caused in the operation of the wrist exerciser. The device includes a ring mounted in a casing of the wrist exerciser and defining diametrically opposite holes that rotatably receive axles of a rotor of the wrist exerciser. A coupler is mounted to an inner circumference of the ring in position corresponding to at least one of the holes. The coupler includes a tube extending in a radial direction of the ring. The tube forms a central bore to rotatably receive the corresponding axle. A plurality of resilient pawls is formed at a free end of the tube and distributed along a circumference of the free end. A balance-enhancing and vibration-reducing element has a central bore fit over the tube of the coupler by elastically deforming the pawls.

Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

Abstract: A heat dissipator fastening kit includes two retaining bars, at least one and as many as three different brackets and multiple fasteners. The retaining bars are resilient, attach to opposite sides of an appropriate heat dissipator and respectively have two ends. The bracket attaches to a motherboard around a CPU and to the retaining bars and has several embodiments to accommodate different types of CPUs, e.g. AM2, K8, LGA775 or P4, and their motherboards. The fasteners attach the retaining bars to a heat dissipator and the bracket and the bracket to a motherboard. With such an arrangement, the heat dissipator fastening kit will be convenient and easy to use.

Abstract: A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: A focusing module includes a casing, at least one fixed magnetic element, a membrane, a movable magnetic element, and a lens. The fixed magnetic element is fixed in the casing for generating a first magnetic field. The membrane is received and retained in an upper section of the casing. The membrane defines a central hole. The movable magnetic element is attached to the membrane, surrounding the central hole of the membrane. The movable magnetic element receives a control signal and in response thereto generates a second magnetic field, which interacts with the first magnetic field of the fixed magnetic field to induce a force acting on the membrane to cause elastic deformation of the membrane. The lens is fixed to the central hole of the membrane whereby the lens is movable with respect to the casing due to the elastic deformation of the membrane caused by magnetic interaction between the first and second magnetic fields of the fixed and movable magnetic elements so as to effect focusing operation.

Abstract: Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 ?m polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 ?m diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 ?m diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 ?m diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 ?m diamond polishing particles.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.