Abstract: Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 ?m polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 ?m diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 ?m diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 ?m diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 ?m diamond polishing particles.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

Abstract: A wrist exerciser includes an upper casing member and a lower casing member that are mounted to each other to enclose a rotor therebetween. The upper casing member has a top opening, which exposes a portion of the rotor. The rotor has opposite sides on which two opposite axles are mounted respectively. The axles are rotatably coupled to an outer ring. The outer ring comprises a resiliency device. The side of the rotor that faces the resiliency device is provided with a movable catching mechanism that is releasably, selectively, and operatively coupled to the resiliency device. Thus, when the rotor is initially rotated or is towed to take a linear movement by being put in contact with a fixture surface, the resiliency device builds up compression spring force, which, when the rotor is released, causes the rotor to rotate in a reversed direction and gaining auxiliary starting power and initial rotation speed.

Abstract: An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.

Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

Abstract: A fuel cell system has fuel cell units, a cycling fuel container with a vent device, a control device, a cycling pump, a fan, a fuel injection device, and an alarm coupled to the control device. The control device monitors a working voltage of the fuel cell system. If the working voltage is detected to be lower than a predetermined low value, the alarm is triggered to inform an operator or user to refill the cycling fuel container by using the fuel injection device.

Abstract: An integrated heat dissipating assembly includes two heat sinks, a heat dissipating fan mounted between the two sinks and a body provided below the two heat sinks and the heat dissipating fan. The body is composed of a hollow body, a pump received inside the hollow body and a base attached to a bottom face of the hollow body for conducting heat from a heat source. The hollow body is divided into receiving spaces respectively communicating with water channels of the two heat sinks such that cooling water flowing inside the hollow body and the water channels of the two heat sinks is able to take away heat from the base. The heat is then dissipated by cool air due to the heat dissipating fan.

Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Abstract: A driving circuit uses a plurality of transformers to provide currents for driving a plurality of LEDs associated with a plurality of current paths. Each transformer has two induction coils with a coil turn ratio between to the number of turns in each induction coil. One induction coil is used to provide an output current to a different current path and the other induction coil is connected to the corresponding induction coil of other transformers for forming a current loop. The output current of each transformer has a relationship with the output current of the other transformers depending on the coil turn ratios of the connected transformers. LEDs in red, blue and green colors can be connected to different current paths so that the brightness of the LEDs in each color can be determined by the current in a current path.

Abstract: A wrist exercise includes a casing composed of upper and lower casing members mating each other to form a hollow sphere, a retention ring fixed between the upper and lower casing members, a rotor rotatably supported inside the casing by the retention ring. Cavities are formed in opposite sides of the rotor and are each divided into chambers by partitions fixed in the cavities. Holes are defined in an outside surface of the rotor and are in communication with the chambers, whereby, in operation of the wrist exerciser, the rotor is rotated and high-speed airflows are caused between the holes and the chambers due to centrifugal forces induced by the rotation of the rotor, which airflows generate sounds, thereby effecting sound generation of the wrist exerciser.

Abstract: Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti) and tungsten nitride (WN); at least one second layer over the first layer, the at least one second layer selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), ruthenium (Ru), rhodium (Rh), platinum (Pt) and cobalt (Co); a seed layer for copper (Cu); and copper (Cu) filling a remaining portion of the opening.

Abstract: A flow board suited for fuel cell applications. The flow board includes a body substrate formed by injection molding methods, which is resistive to methanol or chemical corrosion and has superior mechanical properties. The flow board further includes a wave-shaped reaction zone having thereon a plurality of independent fuel channels. The body substrate and the wave-shaped reaction zone may be monolithic. Alternatively, a punched electrode plate affixed on the reaction zone may define the plurality of independent fuel channels.

Abstract: A wrist exerciser includes an upper casing member and a lower casing member that are mounted to each other to enclose a rotor therebetween. The upper casing member has a top opening, which exposes a portion of the rotor. The rotor has opposite sides on which two opposite axles are mounted respectively. The axles are rotatably coupled to an outer ring. The outer ring comprises a resiliency device. The side of the rotor that faces the resiliency device is provided with a movable catching mechanism that is releasably, selectively, and operatively coupled to the resiliency device. Thus, when the rotor is initially rotated or is towed to take a linear movement by being put in contact with a fixture surface, the resiliency device builds up compression spring force, which, when the rotor is released, causes the rotor to rotate in a reversed direction and gaining auxiliary starting power and initial rotation speed.

Abstract: A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.

Abstract: The present invention provides a DC to DC conversion circuit, comprising a DC power supply, a DC to DC converter, a power management IC and a load, wherein the load may be a backlight source of a liquid crystal display. The power management IC controls the DC to DC converter to convert a DC voltage supplied by the DC power supply to an output voltage of the DC to DC converter, which is supplied to the load. The power management IC is capable of controlling the DC to DC converter to adjust the output voltage to a minimum voltage actually needed by the load according to the variation of the minimum voltage which is actually needed by the load.

Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.