Abstract: A joint includes a plurality of plates each including a first portion and a second portion for overlapping the first portion of the next one of the plates. Each of the plates may define a plurality of apertures each for receiving a fastener. Each of the plates may include a tab formed thereon for connection with an article.

Abstract: A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.

Abstract: Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.

Abstract: A driving circuit uses a plurality of transformers to provide currents for driving a plurality of LEDs associated with a plurality of current paths. Each transformer has two induction coils with a coil turn ratio between to the number of turns in each induction coil. One induction coil is used to provide an output current to a different current path and the other induction coil is connected to the corresponding induction coil of other transformers for forming a current loop. The output current of each transformer has a relationship with the output current of the other transformers depending on the coil turn ratios of the connected transformers. LEDs in red, blue and green colors can be connected to different current paths so that the brightness of the LEDs in each color can be determined by the current in a current path.

Abstract: An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.

Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.

Abstract: Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed metal-silicon (M-Si) on the layer of silicide, then wet etching the metal-silicon. An ozone plasma treatment process can be an option to densify the oxide film. The oxide film may be etched by oxide RIE or wet etch, using 500:1 DHF.

Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

Abstract: Disclosed are pharmaceutical compositions comprising an active vitamin D compound in emulsion pre-concentrate formulations, as well as emulsions and sub-micron droplet emulsions produced therefrom. The compositions comprise a lipophilic phase component, one or more surfactants, and an active vitamin D compound. The compositions may optionally further comprise a hydrophilic phase component.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Abstract: A driving circuit uses a plurality of transformers to provide currents for driving a plurality of LEDs associated with a plurality of current paths. Each transformer has two induction coils with a coil turn ratio between to the number of turns in each induction coil. One induction coil is used to provide an output current to a different current path and the other induction coil is connected to the corresponding induction coil of other transformers for forming a current loop. The output current of each transformer has a relationship with the output current of the other transformers depending on the coil turn ratios of the connected transformers. LEDs in red, blue and green colors can be connected to different current paths so that the brightness of the LEDs in each color can be determined by the current in a current path.

Abstract: A liquid crystal display (LCD) including a light emitting diode (LED) driving circuit and an LED module is provided. The LED module includes a plurality of LEDs. The LED driving circuit includes a transformer, a rectification circuit and a filter circuit. The transformer is used for outputting an AC voltage. The alternate current voltage is respectively rectified and filtered by the rectification circuit and the filter circuit, and then a direct current (DC) voltage level necessary for driving the LEDs is outputted accordingly.

Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Abstract: A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.