Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.

Abstract: A bicycle saddle includes a rigid/semi-rigid shell functioning as a supporting structure for the bicycle saddle. A covering is disposed on the shell and attached thereto, with a padding between the shell and the covering. The padding comprise a cushion made of a resilient material. The cushion includes a plurality of cavities and is attached to the top of the shell such that the cavities would work as pneumatic cushions with air cushions/air springs interposing between the shell and the rider's body.

Abstract: A wrist exercise includes a casing defining an interior space rotatably receiving a rotor. The casing includes upper and lower casing members. The upper casing member has a first mating edge forming a first mating device. The lower casing member has a second mating edge forming a second mating device for mating the first mating device to attach the lower casing member to the upper casing member whereby a circumferential groove is defined between the first and second mating edges. A first retention ring is at least partially fit over the upper and lower casing members and forms an inwardly-projecting portion fit into the groove to securely retain the upper and lower casing members in position.

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: A shell for bicycle saddle includes a body and a shock-absorbing member. The body is made of at least one layer of plastic composite materials (PCM) to form the contour of the shell and has at least one opening corresponding to the sitting area of the bicycle saddle. The shock-absorbing member is made of non plastic composite materials having a hardness lower than that of the body. The shock-absorbing member is filled up the at least one opening of the body to form shock-absorbing zones of the bicycle saddle.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Abstract: A bicycle saddle includes a rigid/semi-rigid shell functioning as a supporting structure for the bicycle saddle. A covering is disposed on the shell and attached thereto, with a padding between the shell and the covering. The padding comprise a cushion made of a resilient material. The cushion includes a plurality of cavities and is attached to the top of the shell such that the cavities would work as pneumatic cushions with air cushions/air springs interposing between the shell and the rider's body.

Abstract: A bicycle saddle is constructed to have a hard bottom shell, a first elastic layer made of foamed plastics and arranged at the top side of the hard bottom shell, a first covering covered on the first elastic layer over the hard bottom shell, and a second elastic layer covered on the first covering, the second elastic layer being formed of a layer of gel arranged at a top side of the first covering and a second covering covered on the layer of gel.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.

Abstract: The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

Abstract: Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

Abstract: A bicycle saddle is constructed to have a hard bottom shell, a first elastic layer made of foamed plastics and arranged at the top side of the hard bottom shell, a first covering covered on the first elastic layer over the hard bottom shell, and a second elastic layer covered on the first covering, the second elastic layer being formed of a layer of gel arranged at a top side of the first covering and a second covering covered on the layer of gel.

Abstract: A cover tape for winding on a grip of a device comprising an elongated cloth layer and an elastic layer. The cloth layer has a first surface and a second surface. The elastic layer is made of silicone gel and bonded to the first surface of the cloth layer for enabling the second surface of the cloth layer to be exposed to the outside when spirally winding the cover tape round the grip with the elastic layer adhered to the periphery of the grip.

Abstract: Disclosed are pharmaceutical compositions comprising an active vitamin D compound in emulsion pre-concentrate formulations, as well as emulsions and sub-micron droplet emulsions produced therefrom. The compositions comprise a lipophilic phase component, one or more surfactants, and an active vitamin D compound. The compositions may optionally further comprise a hydrophilic phase component.

Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.