Patents by Inventor Yusuke Yamashita

Yusuke Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210086519
    Abstract: A recording apparatus includes a carriage configured to move in a width direction intersecting a medium transport direction, a recording head mounted on the carriage, a liquid storage section configured to store a liquid to be supplied to the recording head, the liquid storage section including an injection port configured to receive the liquid from a refill container and a liquid-level visual-check section through which a liquid level of the liquid is visually checked, and a display section configured to accept various setting operations, in which the liquid-level visual-check section and the display section are disposed on an apparatus front surface side, and the display section is disposed above the liquid-level visual-check section.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 25, 2021
    Inventors: Yusuke YAMASHITA, Satoshi KAMINAGA
  • Patent number: 10943745
    Abstract: The electric storage device includes an electrode assembly having a positive electrode and a negative electrode, a case for housing the electrode assembly, a pressure relief valve, and positive and negative electrode conductive members that are electrically connected to the respective corresponding electrodes. The case has a wall in which the pressure relief valve is disposed. At least one of the positive and negative electrode conductive members includes an interposing portion located between the inner surface of the wall and an end face of the electrode assembly facing the inner surface, and a shielding portion located closer to the end face of the electrode assembly than the interposing portion. The shielding portion covers the pressure release valve from a side of the wall where the electrode assembly is located.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 9, 2021
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yusuke Yamashita, Takayuki Hirose, Shinji Suzuki, Yasuaki Takenaka, Masato Ogasawara, Atsushi Minagata, Hirokuni Akiyama, Motoaki Okuda
  • Patent number: 10916751
    Abstract: A power storage apparatus is configured such that a region surrounded by a plane connecting the outline of a pressure release valve and the outline of a tab-side end face in an electrode assembly in the shortest distance is defined as a three-dimensional region. The power storage apparatus is provided with a covering portion that covers the entire cross section of the three-dimensional region along the tab-side end face in a space between the tab-side end face and the inner surface of a lid body.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 9, 2021
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yusuke Yamashita, Takayuki Hirose, Shinji Suzuki
  • Patent number: 10913058
    Abstract: Methods for the removal of ionic contaminants from hydrolysable organic solvent by ion exchange resins are described. A mixed bed of ion exchange resin with cationic ion exchange resin and weak-base anionic ion exchange resin is used in such methods.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 9, 2021
    Assignee: Dow Global Technologies LLC
    Inventors: Kaoru Ohba, Kenji Takano, Masonori Iida, Shinnosuke Abe, Takashi Masudo, Osamu Kishizaki, Ryo Ishibashi, Yusuke Yamashita
  • Publication number: 20210020788
    Abstract: A semiconductor device includes; a schottky diode; a semiconductor substrate that includes a first surface and a second surface opposite to the first surface; a schottky electrode that is placed on the first surface and schottky-contacts to the semiconductor substrate; a first electrode placed on the schottky electrode; and a second electrode that is placed on the second surface and is connected to the semiconductor substrate. The schottky electrode is made of a metal material that is a columnar crystal; and a content of carbon on the schottky electrode is less than 6×1019 cm?3 in at least a part of an area of the schottky electrode.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Inventors: Kouji EGUCHI, Teruaki KUMAZAWA, Yusuke YAMASHITA
  • Publication number: 20200403127
    Abstract: A light-emitting device includes a substrate, an electrode, a light-emitting element, a variable light absorbing layer, and a sealing body. The electrode is formed on the substrate. The light-emitting element is disposed on the substrate and electrically connected to the electrode. The variable light absorbing layer is formed so as to cover the electrode on the substrate. The variable light absorbing layer contains a plurality of metal oxide particles that change a light absorption property by irradiation with an ultraviolet light. The sealing body is formed on the substrate so as to seal the light-emitting element. The sealing body has translucency to a light emitted from the light-emitting element.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 24, 2020
    Inventors: Yusuke Yamashita, Yasuhiro Ono, Yoichi Shimoda
  • Patent number: 10873010
    Abstract: A light-emitting device includes a substrate, a light-emitting element disposed on the substrate, a light transmitting member disposed on the light-emitting element, and a covering body disposed on the substrate. The covering body covers a side surface of the light transmitting member and has an exposed upper surface. A particle group composed of a plurality of particles is dispersed in the covering body. The particle group includes a plurality of titanium oxide particles or zinc oxide particles dispersed in a vicinity of an upper surface of the covering body and each having a portion having a narrower band gap than in other portions of the particle.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 22, 2020
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Yoichi Shimoda, Yasuhiro Ono, Yusuke Yamashita
  • Publication number: 20200381687
    Abstract: A power storage apparatus is configured such that a region surrounded by a plane connecting the outline of a pressure release valve and the outline of a tab-side end face in an electrode assembly in the shortest distance is defined as a three-dimensional region. The power storage apparatus is provided with a covering portion that covers the entire cross section of the three-dimensional region along the tab-side end face in a space between the tab-side end face and the inner surface of a lid body.
    Type: Application
    Filed: February 27, 2018
    Publication date: December 3, 2020
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yusuke YAMASHITA, Takayuki HIROSE, Shinji SUZUKI
  • Patent number: 10845357
    Abstract: A fixed region at an outer periphery or an inner periphery of a sample that has a three-dimensional structure is selectively analyzed with accuracy. Provided is an observation system including a CPU that recognizes the 3D shape of an observation target, such as a spheroid, from a 3D image of cells, that sets a 3D mask of which the radial distance from a circumscribed surface of the recognized 3D shape is fixed over the entire region of the circumscribed surface and of which the shape is similar to the circumscribed surface, and that identifies a cell contained inside the set 3D mask.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 24, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Yusuke Yamashita
  • Patent number: 10840386
    Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 17, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hiroki Miyake, Yasushi Urakami, Yusuke Yamashita
  • Publication number: 20200344431
    Abstract: An imaging apparatus having a wide dynamic range and a stable black level without decreasing frame rate comprises a pixel unit including pixels, a read out unit for reading out the noise signal from each pixel and to amplify the noise signal by a first gain to generate a first noise signal, reads out the pixel signal and amplifies the pixel signal by the first gain and a second gain to generate a first and a second pixel signal, a first memory unit for storing a second noise signal generated by amplifying, by the second gain, the noise signal read out from a pixel of a predetermined row, and a subtraction unit for subtracting the first noise signal from the first pixel signal and to subtract the second noise signal stored in the first memory unit from the second pixel signal, while sequentially reading out signals from each pixel.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 29, 2020
    Inventors: Takenori Kobuse, Yusuke Yamashita
  • Patent number: 10791295
    Abstract: A photoelectric conversion apparatus includes first and second signal lines, first and second circuits, and a switch. Signals based on electric charges generated in first and second photoelectric conversion portions are to be read out to the first and second signal lines, respectively. The first circuit includes a first input unit to which the first signal line is connected. The first circuit is configured to perform processing of a signal input to the first input unit, with a first gain. The second circuit includes a second input unit to which the second signal line is connected. The second circuit is configured to perform processing of a signal input to the second input unit. The switch is configured to perform switching between a connected state and a disconnected state between the first signal line and the second signal line.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 29, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shoji Kono, Toru Koizumi, Hiroo Akabori, Yusuke Yamashita
  • Publication number: 20200303702
    Abstract: This power storage apparatus has a case accommodating an electrode assembly and an electrolytic solution, and a release valve present in the wall of the case. The electrode assembly includes electrodes which have different polarities and are insulated from each other. A shielding member is arranged between the inner surface of the wall and the end surface of the electrode assembly. A point located in a center of the case in a front view of the case taken in the stacking direction of the electrodes and located in a center of a dimension of the electrode assembly in the stacking direction is referred to as a center point, and a region surrounded by a plane connecting the center point and a contour of the pressure release valve at a shortest distance is referred to as a three-dimensional region. The shielding member includes a shielding portion that entirely covers a cross section of the three-dimensional region along the end face of the electrode assembly.
    Type: Application
    Filed: March 31, 2017
    Publication date: September 24, 2020
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Tomohiro NAKAMURA, Takayuki HIROSE, Yusuke YAMASHITA, Masato OGASAWARA, Shinji SUZUKI, Yasuaki TAKENAKA, Ryuji OIDE, Mikiya KURITA, Atsushi MINAGATA
  • Patent number: 10720492
    Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 21, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Shuhei Mitani, Katsumi Suzuki, Yusuke Yamashita
  • Publication number: 20200220008
    Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Inventors: Yuichi TAKEUCHI, Yasuhiro EBIHARA, Masahiro SUGIMOTO, Yusuke YAMASHITA
  • Publication number: 20200203482
    Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 25, 2020
    Inventors: Aiko KAJI, Yuichi TAKEUCHI, Shuhei MITANI, Ryota SUZUKI, Yusuke YAMASHITA
  • Patent number: 10690902
    Abstract: Visual observation of morphological features of a cell group or individual cells acquired in 3D image data is facilitated, thus improving observation accuracy. Provided is an image processing device that generates, on the basis of a plurality of 2D images acquired by a microscope at different focus positions on a cell clump, 3D images of respective cells constituting the cell clump, that processes the generated 3D images and analyzes feature amounts on the basis of at least one measurement parameter, that displays analysis results in a graph, that allows a user to select a region of interest on the displayed graph, and that generates, from the 3D images that correspond to the plurality of cells that are included in the selected region of interest, 2D display images each in a plane with reference to an axis that is determined on the basis of a shape feature of the corresponding cell and displays the 2D display images in a list.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 23, 2020
    Assignee: OLYMPUS CORPORATION
    Inventors: Hisao Kitagawa, Yusuke Yamashita
  • Publication number: 20200185574
    Abstract: A light-emitting device having high output and high contrast with simple configuration is provided. The light-emitting device includes a substrate, a light-emitting element disposed on the substrate, a light-transmitting member disposed on the light-emitting element, and a covering body disposed on the substrate so as to surround the light-transmitting member and cover a side surface of the light-transmitting member. The covering body has a particle group including a plurality of metal oxide particles having a light scattering property and dispersed in the covering body, and the metal oxide particles existing in the vicinity of the side surface of the covering body have a portion having a bandgap smaller than that of other portions in each particle.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Yoichi SHIMODA, Yasuhiro ONO, Yusuke YAMASHITA
  • Publication number: 20200161467
    Abstract: A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.
    Type: Application
    Filed: December 30, 2019
    Publication date: May 21, 2020
    Inventors: Yuichi TAKEUCHI, Shuhei MITANI, Yasuhiro EBIHARA, Yusuke YAMASHITA, Tadashi MISUMI
  • Patent number: 10658503
    Abstract: Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 19, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yusuke Yamashita, Satoru Machida, Takahide Sugiyama, Jun Saito