Patents by Inventor Yusuke Yamashita

Yusuke Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200152542
    Abstract: A semiconductor device may include a semiconductor substrate, an insulator film covering a part of an upper surface of the substrate, and a gate electrode opposing the upper surface via the insulator film. In the semiconductor substrate, a drift layer extending through a body layer to the upper surface opposes the gate electrode via the insulator film. The insulator film extends from the upper surface of the semiconductor substrate to an upper surface of the gate electrode by passing between the gate electrode and an upper electrode, and defines an opening at the upper surface of the gate electrode. In a first region being a set of straight lines where each line extends through an opposing surface of the drift layer that opposes the gate electrode perpendicularly to the opposing surface, the insulator film does not exist on the upper surface of the gate electrode.
    Type: Application
    Filed: October 29, 2019
    Publication date: May 14, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun SAITO, Yusuke Yamashita, Yasushi Urakami
  • Patent number: 10638066
    Abstract: An apparatus including: first and second photoelectric converting portions; a charge detecting portion; a transistor outputting a pixel signal; first and second sampling and holding capacitors; an amplifier; and a controlling unit controlling gain in first and second mode. The pixel signal is one of: a first signal at a time of resetting of charge; a second signal including a charge component of the first photoelectric converting portion and a noise component; and a third signal including the first component, a charge component of the second photoelectric converting portion, and a noise component. In the first mode, the controlling unit uses a first gain. In the second mode, the controlling unit uses second gain to the first signal, third gain to the third signal of the first sampling and holding capacitor, and second gain to the third signal of the second sampling and holding capacitor.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 28, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kobayashi, Shoji Kono, Yusuke Yamashita
  • Patent number: 10593750
    Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate including a foundation layer having a first conductivity type; forming a deep trench in the foundation layer; and forming a deep layer having a second conductivity type by introducing material gas of the compound semiconductor while introducing dopant gas into an epitaxial growth equipment to cause epitaxial growth of the deep layer in the deep trench. A period in which a temperature in the epitaxial growth equipment is increased to a temperature of the epitaxial growth of the deep layer is defined as a temperature increasing period. In the forming the deep layer, the deep layer is further formed in a bottom corner portion of the deep trench by starting the introducing of the dopant gas during the temperature increasing period and starting the introducing of the material gas after the temperature increasing period.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 17, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Katsumi Suzuki, Yusuke Yamashita
  • Patent number: 10580851
    Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate that includes a foundation layer; forming a deep trench in the foundation layer; and filling the deep trench with a deep layer having a second conductive type and a limiting layer having the first conductive type. In the filling the deep trench, growth of the deep layer from a bottom of the deep trench toward an opening inlet of the deep trench and growth of the limiting layer from a side face of the deep trench are achieved by: dominant epitaxial growth of a second conductive type layer over a first conductive type layer on the bottom of the deep trench; and dominant epitaxial growth of the first conductive type layer over the second conductive type layer on the side face of the deep trench, based on plane orientation dependency of the compound semiconductor during epitaxial growth.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 3, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Katsumi Suzuki, Yusuke Yamashita
  • Publication number: 20200043823
    Abstract: A semiconductor device includes a semiconductor substrate comprising an upper surface and a lower surface, an upper electrode provided on the upper surface, and a lower electrode provided on the lower surface. The semiconductor substrate includes, in a planar view, a first section including a center of the semiconductor substrate and a second section located between the first section and a peripheral edge of the semiconductor substrate. The first and second sections each comprise a MOSFET structure including a body diode. The MOSFET structure in the first section and the MOSFET structure in the second section are different from each other such that a forward voltage drop of the body diode in the first section with respect to a current density is higher than a forward voltage drop of the body diode in the second section with respect to the current density.
    Type: Application
    Filed: January 26, 2018
    Publication date: February 6, 2020
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Tatsuji NAGAOKA, Yusuke YAMASHITA, Yasushi URAKAMI
  • Publication number: 20200044018
    Abstract: A semiconductor device (10) includes a semiconductor substrate (12) including an element region (20) and an outer-periphery voltage withstanding region (22). The outer-periphery voltage withstanding region includes a plurality of p-type guard rings (40) surrounding the element region (20) in a multiple manner. Each of the guard rings (40) includes a high concentration region (42) and a low concentration region (44). A low concentration region of an outermost guard ring includes a first part (51x) positioned on an outer peripheral side of its high concentration region. Respective low concentration regions of the guard rings include respective second parts (52) each positioned in a range sandwiched between corresponding two adjacent high concentration regions among a plurality of concentration regions. A width of the first part on a front surface (12a) is wider than widths of the second parts on the front surface.
    Type: Application
    Filed: September 26, 2017
    Publication date: February 6, 2020
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hiromichi KINPARA, Yusuke YAMASHITA, Yasushi URAKAMI
  • Patent number: 10552945
    Abstract: A sample observation apparatus includes a memory and a main controller. The main controller stores a first number of photoelectrons required in a raw image for generating a super-resolution image. The main controller calculates the number of image data sets to be added together for generating the raw image based on the first number of photoelectrons stored in the memory and a predetermined image acquisition condition, acquires multiple sets of image data of the same region of a sample by repeatedly detecting light from the same region based on the calculated number of image data sets, and generates the raw image by adding together the acquired multiple sets of image data of the same region.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 4, 2020
    Assignee: OLYMPUS CORPORATION
    Inventors: Hisao Kitagawa, Yusuke Yamashita, Yasunari Matsukawa
  • Patent number: 10546933
    Abstract: A switching element may include a SiC substrate including an off-angle; a trench provided in an upper surface of the SiC substrate and extending along an off-direction of the SiC substrate in a plan view of the upper surface; a gate insulating film; and a gate electrode. The SiC substrate may include a source region of n-type; a contact region of p-type; a body region of p-type being in contact with the gate insulating film below the source region; a drift region of n-type being in contact with the gate insulating film below the body region; and low lifetime regions located in a range between the drift region and at least one of the source region and the contact region. The low lifetime regions may be arranged along the off-direction with intervals, and at least a part of the body region may be provided in the intervals.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 28, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Katsunori Danno, Kensaku Yamamoto, Yusuke Yamashita
  • Patent number: 10538095
    Abstract: There is provided a printer that functions as a droplet ejecting apparatus including: a tank which is configured of at least a part having light transmission property; a tank cover which functions as a cover portion that covers the tank; and a light transmitting portion which is provided at least at a part of the tank cover, and through which liquid accommodated on the inside of the tank can be visually confirmed, in which at least one of gradations and reference marks is provided in the light transmitting portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 21, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Tanaka, Koji Kawai, Tomoyuki Higuchi, Ichiro Yoshioka, Yusuke Yamashita, Masahide Nakagawa
  • Publication number: 20200020814
    Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.
    Type: Application
    Filed: November 28, 2017
    Publication date: January 16, 2020
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hiroki MIYAKE, Yasushi URAKAMI, Yusuke YAMASHITA
  • Publication number: 20190393386
    Abstract: A light-emitting device comprises: a substrate; a light-emitting element disposed on the substrate; a light transmitting member disposed on the light-emitting element; and a covering body that is disposed on the substrate, covers a side surface of the light transmitting member and has an upper surface exposed to the outside. In this device, the covering body has a particle group composed of a plurality of particles dispersed in the covering body, and the particle group includes a plurality of titanium oxide particles or zinc oxide particles dispersed in the vicinity of the upper surface of the covering body and having a portion having a narrower band gap than that in other portions in each particle.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 26, 2019
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Yoichi SHIMODA, Yasuhiro ONO, Yusuke YAMASHITA
  • Publication number: 20190386094
    Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.
    Type: Application
    Filed: June 29, 2017
    Publication date: December 19, 2019
    Inventors: Yuichi TAKEUCHI, Shuhei MITANI, Katsumi SUZUKI, Yusuke YAMASHITA
  • Patent number: 10466459
    Abstract: A microscope system includes a scanner that scans laser light emitted from a continuous-wave light source on a specimen, a beam splitter that splits fluorescence from the specimen into a plurality of light paths with the same wavelength, a plurality of PMTs that respectively detect the fluorescence in the light paths and output light intensity signals, and a computer. Each time the laser light is repeatedly scanned by the scanner, the computer acquires, for each of the PMTs, an image dataset of the specimen based on the light intensity signals. The computer combines a plurality of the image datasets for the same area of the specimen and subjects a final combined image dataset to computational processing for enhancing high-frequency components.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 5, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Yusuke Yamashita
  • Patent number: 10468520
    Abstract: A switching element may include a semiconductor substrate, a trench, a gate insulating film, and a gate electrode. A drift region may be in contact with the gate insulating film below the body region. A bottom region may be in contact with the gate insulating film at a bottom surface of the trench. A connection region may be in contact with the gate insulating film at a side surface of the trench and connect the body region and the bottom region. The side surface of the trench may include a first side surface and a second side surface positioned below the first side surface. An inclination angle of the second side surface may be larger than an inclination angle of the first side surface. An interface between the body region and the drift region may be in contact with the gate insulating film at the first side surface.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 5, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiromichi Kinpara, Yusuke Yamashita, Kensaku Yamamoto
  • Publication number: 20190319056
    Abstract: An image sensor comprises: a pixel region including a plurality of microlenses arranged in a matrix, and a plurality of photoelectric conversion portions provided for each of the microlenses; a plurality of amplifiers that apply a plurality of different gains to signals output from the pixel region; and a scanning circuit that scans the pixel region so that a partial signal and an added signal are read out, the partial signal being a signal from some of the plurality of photoelectric conversion portions, and the added signal being a signal obtained by adding the signals from the plurality of photoelectric conversion portions.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Inventors: Yusuke Yamashita, Koki Nakamura
  • Patent number: 10439037
    Abstract: A method for manufacturing a compound semiconductor device includes causing epitaxial growth of a p-type impurity layer containing a compound semiconductor on a foundation layer containing the compound semiconductor. The causing the epitaxial growth includes performing pre-doping to preliminarily introduce dopant gas before introducing material gas for the epitaxial growth of the compound semiconductor. The dopant gas contains an organic metal material providing dopant of p-type impurities. An impurity concentration profile of the p-type impurity layer is controlled by controlling a time of the pre-doping.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 8, 2019
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Katsumi Suzuki, Yusuke Yamashita
  • Patent number: 10417482
    Abstract: Provided is an observation system including: a monitor; a CPU that identifies, in a 3D image including the plurality of cells, the respective cells by assigning labels that differ from one another to the respective cells, that associates three mutually-intersecting cross-sectional images that constitute the 3D image, and that simultaneously displays the cross-sectional images on the monitor; and an input unit with which an operator specifies an arbitrary cell in any of the cross-sectional images displayed on the monitor. The CPU extracts, from the 3D image, the cross-sectional shapes, in the respective cross-sectional images, of the cell specified by using the input unit, on the basis of the labels, associates the extracted cross-sectional shapes of the cell with one another, and displays the extracted cross-sectional shapes in the respective cross-sectional images displayed on the monitor, in a distinguishable manner from the other cells.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 17, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Yusuke Yamashita
  • Publication number: 20190246054
    Abstract: Provided is an apparatus including: first and second photoelectric converting portions; a charge detecting portion; a transistor outputting a pixel signal first and second sampling and holding capacitors; an amplifier; and a controlling unit controlling gain in first and second mode. The pixel signal is one of: a first signal at time of resetting of charge; a second signal including a charge component of the first photoelectric converting portion and a noise component; and a third signal including the first component, a charge component of the second photoelectric converting portion and a noise component. In the first mode, the controlling unit uses a first gain. In the second mode, the controlling unit uses second gain to the first signal, third gain to the third signal of the first sampling and holding capacitor, and second gain to the third signal of the second sampling and holding capacitor.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 8, 2019
    Inventors: Masahiro Kobayashi, Shoji Kono, Yusuke Yamashita
  • Patent number: D864289
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 22, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Tomoyuki Higuchi, Yusuke Yamashita, Ichiro Yoshioka, Natsumi Watarai
  • Patent number: D873342
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 21, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yusuke Yamashita