Semiconductor package assembly
In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
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This application is a Continuation of pending U.S. patent application Ser. No. 15/014,636, filed Feb. 3, 2016, which claims the benefit of U.S. Provisional Application No. 62/133,680 filed Mar. 16, 2015, the entireties of which are incorporated by reference herein.
BACKGROUND OF THE INVENTIONField of the Invention
The present invention relates to a semiconductor package assembly, and in particular to a semiconductor package assembly with a passive device.
Description of the Related Art
In order to ensure miniaturization and multi-functionality of electronic products and communication devices, it is desired that semiconductor packages be small in size, support multi-pin connection, operate at high speeds, and have high functionality. A conventional semiconductor package usually places passive devices on a printed circuit board (PCB). However, the PCB is required to provide additional area for the passive devices mounted thereon. It is hard to reduce the package size.
Thus, a novel semiconductor package assembly is desirable.
BRIEF SUMMARY OF THE INVENTIONA semiconductor package assembly is provided. An exemplary embodiment of a semiconductor package assembly includes
1. A semiconductor package assembly, comprising: a first semiconductor package, having: a first semiconductor die, and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
Another exemplary embodiment of a semiconductor package assembly includes a first semiconductor package, having: a first semiconductor die, and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes: a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer disposed between the first conductive trace and the second conductive trace, and a capacitor structure composed of the first conductive trace, the second conductive trace and the second inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
Yet another exemplary embodiment of a semiconductor package assembly includes a first semiconductor package, having a first semiconductor die, and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer between the first conductive trace and the second conductive trace, and a capacitor structure composed of the first conductive trace, the second conductive trace and the second inter-metal dielectric (IMD) layer, wherein the thickness of the second inter-metal dielectric (IMD) layer is less than or equal to those of the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by reference to the appended claims.
The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.
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In some embodiments, the semiconductor package assembly 500a is designed to fabricate a passive device structure, for example, a metal-insulator-metal (MIM) capacitor structure 450a embedded in a redistribution layer (RDL) structure 308. The MIM capacitor structure 450a is composed segments of conductive traces (the first electrode 452a-1 and the second electrode 454a-1) of the RDL structure 308 and a high-k capacitor dielectric material layer (the IMD layer 456a) beside the IMD layer (the IMD layer 318) of the RDL structure 308. The capacitor structure 450a is designed to increase the dielectric constant (k) of the IMD layer 456a, or to decrease the thicknesses of the first electrode 452a-1 (the thickness T1), the second electrode 454a-1 (the thickness T2) and the IMD layer 456a (the thickness T3), so that the larger capacitance value is obtained. The embedded MIM capacitor structure 450a can be integrated with the RDL structure 308 and using a process similar to the fabrication process of the RDL structure 308. The MIM capacitor structure 450a may provide comparable process capability in the semiconductor package assembly. Also, the semiconductor package assembly 500a may help to improve the surface-mount technology (SMT) yield even when the semiconductor die (the SOC die 302) is replaced. Additionally, the signal integrity/power integrity (SI/PI) performance of the embedded MIM capacitor structure 450a can be improved due to the shortened routing path between the semiconductor die (the SOC die 302) and the MIM capacitor structure 450a. The embedded MIM capacitor structure 450a can provide design flexibility for the system integration of the semiconductor package assembly 500a.
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In some embodiments, the semiconductor package assembly 500b is designed to fabricate a passive device structure, for example, a metal-insulator-metal (MIM) capacitor structure 450b embedded in a redistribution layer (RDL) structure 308 of the semiconductor package 300b. The advantages of the semiconductor package assembly 500b are similar to those of the semiconductor package assembly 500a. Also, the capacitor structure 450b is designed to have zigzag-shaped electrodes (the first electrode 452b-1 and the second electrode 454b-1) and a zigzag-shaped capacitor dielectric layer (the IMD layer 456b) to increase the area of the capacitor structure 450b, so that the larger capacitance value is obtained. Additionally, the capacitor structure 450b is designed to increase the dielectric constant (k) of the IMD layer 456b, or to decrease the thicknesses of the first electrode 452b-1 (the thickness T1), the second electrode 454b-1 (the thickness T2) and the IMD layer 456b (the thickness T3) to obtain the larger capacitance value.
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Like the RDL structure 308, the RDL structure 328 may have one or more conductive traces 336 disposed in one or more inter-metal dielectric (IMD) layers 334. Pad portions of the conductive traces 336 are exposed to openings of one the IMD layers 334, which is away from the surface 354 of the molding compound 350. However, it should be noted that the number of conductive traces 336 and the number of IMD layers 328 shown in
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The pads 408 and 410 of the semiconductor dies 402 and 404 may be coupled to pads 425 of the RDL structure 418 by bonding wires, for example bonding wires 414 and 416, respectively. However, the number of stacked semiconductor dies is not limited to the disclosed embodiment. Alternatively, the two semiconductor dies 402 and 404 shown in
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The sorts of semiconductor dies are not limited to the disclosed embodiment. For example, in some embodiments, the semiconductor die 302 can be a baseband chip, another semiconductor 402 or 404 can be a RF (radio-frequency) chip. In other some embodiments, the semiconductor die 302 can be a AP (analog processor) chip, another semiconductor die 402 or 404 can be a DP (digital processor) chip.
Embodiments provide a semiconductor package assembly. In some embodiments, the semiconductor package assembly is designed to fabricate a passive device structure, for example, a metal-insulator-metal (MIM) capacitor structure embedded in and integrated with a redistribution layer (RDL) structure. The MIM capacitor structure is composed segments of conductive traces (serving as the first electrode and the second electrode) of the RDL structure and a high-k capacitor dielectric material layer (k≥20) beside the low-k IMD layer (k≈4) of the RDL structure. The capacitor structure is designed to increase the dielectric constant (k) of the high-k capacitor dielectric material layer, or to decrease the thicknesses of the first electrode, the second electrode and the high-k capacitor dielectric material layer, so that the larger capacitance value is obtained. Alternatively, the capacitor structure is designed to have zigzag-shaped electrodes and a zigzag-shaped capacitor dielectric layer to increase the area of the capacitor structure, thereby increasing the capacitance value. The fabrication process of embedded MIM capacitor structure can be integrated with that of the RDL structure. Therefore, the MIM capacitor structure may provide the comparable process capability. Therefore, the MIM capacitor structure may provide the comparable process capability. Also, the semiconductor package assembly may help to improve the surface-mount technology (SMT) yield even when the semiconductor die (the SOC die) is replaced. Additionally, the signal integrity/power integrity (SI/PI) performance of the embedded MIM capacitor structure can be improved due to the shortened routing path between the semiconductor die (the SOC die) and the MIM capacitor structure. The embedded MIM capacitor structure can provide the design flexibility for the system integration of the semiconductor package assembly.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A semiconductor package assembly, comprising:
- a first semiconductor package, comprising:
- a first semiconductor die; and
- a first redistribution layer (RDL) structure coupled to the first semiconductor die, wherein the first redistribution layer (RDL) structure comprises: a first conductive trace at a first layer-level; a second conductive trace at a second layer-level; and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shaped in a cross-sectional view, wherein a first portion of the first conductive trace and a second portion of the second conductive trace are in contact with the second inter-metal dielectric (IMD) layer.
2. The semiconductor package assembly as claimed in claim 1, wherein the first semiconductor package comprises:
- a first molding compound surrounding the first semiconductor die; and
- first conductive structures disposed on and coupled to the first RDL structure.
3. The semiconductor package assembly as claimed in claim 2, wherein the first conductive trace is disposed close to the first semiconductor die, wherein the second conductive trace is disposed close to the first conductive structures.
4. The semiconductor package assembly as claimed in claim 1, wherein the first conductive trace is separated from the second conductive trace.
5. The semiconductor package assembly as claimed in claim 1, wherein the dielectric constant of the first inter-metal dielectric (IMD) layer is lower than the dielectric constant of the second inter-metal dielectric (IMD) layer.
6. The semiconductor package assembly as claimed in claim 5, wherein of a first thickness of the first inter-metal dielectric (IMD) layer is greater than a second thickness of the second inter-metal dielectric (IMD) layer in a cross-sectional view.
7. The semiconductor package assembly as claimed in claim 1, wherein the first portion of the first conductive trace and the second portion of the second conductive trace, which are in contact with the second inter-metal dielectric (IMD) layer, are zigzag shaped in the cross-sectional view.
8. The semiconductor package assembly as claimed in claim 1, wherein the first semiconductor package comprises:
- a second redistribution layer (RDL) structure disposed on the first semiconductor die, wherein the first molding compound has two opposite surfaces in contact with the first RDL structure and the second RDL structure, respectively; and
- first vias passing through the first molding compound between the first RDL structure and the second RDL structure, wherein the first vias surround the first semiconductor die.
9. The semiconductor package assembly as claimed in claim 1, wherein the first semiconductor package further comprises:
- a second semiconductor die coupled to the first RDL structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side.
10. The semiconductor package assembly as claimed in claim 9, further comprising:
- a second semiconductor package stacked on the first semiconductor package, comprising:
- a third redistribution layer (RDL) structure;
- a second semiconductor die coupled to the third RDL structure; and
- a second molding compound surrounding the second semiconductor die, being in contact with the third RDL structure and the second semiconductor die.
11. The semiconductor package assembly as claimed in claim 10, wherein the second RDL structure is disposed between the first RDL structure and the third RDL structure.
12. The semiconductor package assembly as claimed in claim 10, wherein the second semiconductor package comprises:
- second conductive structures disposed on a surface of the third RDL structure, which is away from the second semiconductor die, wherein the second conductive structures are coupled to the third RDL structure.
13. The semiconductor package assembly as claimed in claim 10, wherein the first semiconductor package is a system-on-chip (SOC) package, and the second semiconductor package is a DRAM package.
14. The semiconductor package assembly as claimed in claim 10, wherein the second semiconductor package further comprises:
- a third semiconductor die coupled to the third RDL structure, wherein the second semiconductor die and the third semiconductor die are arranged side-by-side.
15. A semiconductor package assembly, comprising:
- a first semiconductor package, comprising:
- a first semiconductor die; and
- a first redistribution layer (RDL) structure coupled to the first semiconductor die, wherein the first redistribution layer (RDL) structure comprises:
- a first conductive trace at a first layer-level;
- a second conductive trace at a second layer-level;
- a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer disposed between the first conductive trace and the second conductive trace; and
- a capacitor structure composed of the first conductive trace, the second conductive trace and the second inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is zigzag shaped in a cross-sectional view,
- wherein a first portion of the first conductive trace and a second portion of the second conductive trace are in contact with the second inter-metal dielectric (IMD) layer.
16. The semiconductor package assembly as claimed in claim 15, wherein the second inter-metal dielectric (IMD) layer is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace.
17. The semiconductor package assembly as claimed in claim 15, wherein the first semiconductor package comprises:
- a first molding compound surrounding the first semiconductor die;
- first vias passing through the first molding compound, wherein the first vias surround the first semiconductor die; and
- first conductive structures disposed on and coupled to the first RDL structure.
18. The semiconductor package assembly as claimed in claim 15, wherein of a first thickness of the first inter-metal dielectric (IMD) layer is greater than a second thickness of the second inter-metal dielectric (IMD) layer in a cross-sectional view.
19. A semiconductor package assembly, comprising:
- a first semiconductor package, comprising:
- a first semiconductor die; and
- a first redistribution layer (RDL) structure coupled to the first semiconductor die, wherein the first redistribution layer (RDL) structure comprises:
- a first conductive trace at a first layer-level;
- a second conductive trace at a second layer-level;
- a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer between the first conductive trace and the second conductive trace; and
- a capacitor structure composed of the first conductive trace, the second conductive trace and the second inter-metal dielectric (IMD) layer, wherein the thickness of the second inter-metal dielectric (IMD) layer is less than or equal to those of the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shaped in a cross-sectional view,
- wherein a first portion of the first conductive trace and a second portion of the second conductive trace are in contact with the second inter-metal dielectric (IMD) layer.
20. The semiconductor package assembly as claimed in claim 19, wherein the first semiconductor package comprises:
- a second redistribution layer (RDL) structure disposed on the first semiconductor die, wherein the first molding compound has two opposite surfaces in contact with the first RDL structure and the second RDL structure, respectively.
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Type: Grant
Filed: Jun 9, 2017
Date of Patent: Jan 8, 2019
Patent Publication Number: 20170278832
Assignee: MediaTek Inc. (Hsin-Chu)
Inventors: Tzu-Hung Lin (Zhubei), I-Hsuan Peng (Hsinchu), Ching-Wen Hsiao (Hsinchu)
Primary Examiner: Dao H Nguyen
Application Number: 15/618,210
International Classification: H01L 25/16 (20060101); H01L 25/10 (20060101); H01L 23/485 (20060101); H01L 23/31 (20060101); H01L 23/00 (20060101); H01L 25/065 (20060101); H01L 23/538 (20060101); H01L 23/498 (20060101);