Semiconductor processing station

A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

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Description
CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser. No. 14/996,231, filed on Jan. 15, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

In recent years, the semiconductor processing station has been an important development in semiconductor manufacturing. Multiple substrates (e.g. wafers) are typically stored and transported together in batches by a transport carrier throughout a semiconductor fabrication facility (“fab”) between load ports of different wafer processing tools or equipments. Such tools generally perform various photolithography, etching, material/film deposition, curing, annealing, inspection, or other processes used in IC chip manufacturing. One such transport carrier is a front opening unified pod (FOUP) which is a plastic enclosure designed to hold a plurality of substrates in a controlled environment.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic plan view of a semiconductor processing station according to some embodiments of the present disclosure.

FIG. 2 is a schematic side view of the semiconductor processing station of FIG. 1 according to some embodiments of the present disclosure.

FIG. 3 through FIG. 9 are schematic front views of the semiconductor processing station in FIG. 1 illustrating load process of the transport carrier according to some embodiments of the present disclosure.

FIG. 10 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure.

FIG. 11 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure.

FIG. 12 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure.

FIG. 13 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure.

FIG. 14 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure.

 DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG. 1 is a schematic plan view of a semiconductor processing station according to some embodiments of the present disclosure. FIG. 2 is a schematic side view of the semiconductor processing station of FIG. 1 according to some embodiments of the present disclosure.

Referring to FIG. 1 and FIG. 2, a semiconductor processing station 10 is configured to process a substrate 12, such as a wafer. The substrate 12 may include one or more semiconductor, conductor, and/or insulator layers. The semiconductor layers may include an elementary semiconductor such as silicon or germanium with a crystalline, polycrystalline, amorphous, and/or other suitable structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; any other suitable material; and/or combinations thereof. In some embodiments, combinations of semiconductors may take the form of a mixture or gradient such as a substrate in which the ratio of Si and Ge vary across locations. In some embodiments, the substrate 12 may include layered semiconductors. Examples include the layering of a semiconductor layer on an insulator such as that used to produce a silicon-on-insulator (“SOI”) substrate, a silicon-on-sapphire substrate, or a silicon-germanium-on-insulator substrate, or the layering of a semiconductor on glass to produce a thin film transistor (“TFT”).

The semiconductor processing station 10 includes a platform 100 and a load port 200. The platform 100 includes an intake/outtake port 110, a plurality of processing modules 120 and a central transfer module 130 with a central transfer mechanism 132. The intake/outtake port 110 and the plurality of processing modules 120 are arranged in the periphery of the central transfer module 130. This configuration allows the central transfer mechanism 132 to transport the substrate 12 between the processing modules 120 and the intake/outtake port 110.

The processing modules 120 may be configured to perform any manufacturing procedure on the substrate 12. Substrate manufacturing procedures include deposition processes such as physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), plasma-enhanced chemical vapor deposition (“PECVD”), electrochemical deposition (“ECD”), molecular beam epitaxy (“MBE”), atomic layer deposition (“ALD”) and/or other deposition processes; etching processes including wet and dry etching and ion beam milling; lithographic exposure; ion implantation; thermal processes such as annealing and/or thermal oxidation; cleaning processes such as rinsing and/or plasma ashing; chemical mechanical polishing or chemical mechanical planarizing (collectively “CMP”) processes; testing; any procedure involved in the processing of the substrate 12; and/or any combination of procedures.

The area of the semiconductor processing station 10 defined by the platform 100 including the intake/outtake port 110, the plurality of processing modules 120 and the central transfer module 130 is sealed. Atmospheric controls, including filtering, provide an environment with extremely low levels of particulates and airborne molecular contamination (“AMC”). By creating a microenvironment within the semiconductor processing station 10, the processing modules 120 can be operated in a cleaner environment than the surrounding facilities. This allows tighter control of contaminates during substrate processing at reduced cost.

The load port 200 includes a load chamber 210 and a carrier transfer module 220 in the load chamber 210. The load chamber 210 communicates with the intake/outtake port 110 of the platform 100. The load chamber 210 has a load opening 212 at its top end 214 for receiving a transport carrier 300 within the load chamber 210. Furthermore, a movable cover 230 is disposed at the load opening 212 and can be configured to open or seal the load opening 212 of the load chamber 210. In some embodiments, the transport carrier 300 may be a front-opening unified pod (“FOUP”), a front-opening shipping box (“FOSB”), a standard mechanical interface (“SMIF”) pod, and/or other suitable container. The transport carrier 300 can be loaded within the load chamber 210 through the load opening 212 at the top end 214 of the load chamber 210. Then, the carrier transfer module 220 can transfer the transport carrier 300 to the intake/outtake port 110. Herein, the position of the transport carrier 300 may be adjusted by the carrier transfer module 220 to effectively couple the transport carrier 300 to the intake/outtake port 110. For example, the transport carrier 300 may move in a specific distance and turns in a small angle to exactly face the intake/outtake port 110.

In some embodiments, the load opening 212 can be sealed by the movable cover 230 to form a vacuum environment for containing the transport carrier 300. A vacuum pump 240 may be disposed at the bottom end 216 of the load chamber to form the vacuum environment. The load chamber 210 together with the intake/outtake port 110 preserves the atmosphere within the central transfer module 130 and the processing modules 120 by separating them from the outside environment by sealing the load chamber 210.

In further other embodiments, the load chamber 210 is capable of creating an atmosphere compatible with outside environment or the central transfer chamber 14 depending on where the transport carrier 300 is scheduled to be next. This may require altering the gas content of the load chamber 210 by such mechanisms as adding purified gases or creating a vacuum, along with other suitable means for adjusting the load lock chamber atmosphere. When the correct atmosphere has been reached, the transport carrier 300 may be opened, and the substrates 12 in the transport carrier 300 can be accessed and transferred to the processing modules 120 by the central transfer module 130; alternatively, the transport carrier 300 with the processed substrates 12 may be removed from the load chamber 210 through the load opening 212.

In some embodiments, the central transfer module 130 communicates with the intake/outtake port 110 and the plurality of processing modules 120. A substrate transfer mechanism 132 is configured in the central transfer module 130 to pick up and traversely transfer the plurality of substrates 12 from the transport carrier 300 to the processing modules 120 in sequence. Furthermore, in some embodiments, the carrier transfer module 220 may include a carrier lift mechanism 222 configured to move the transport carrier 300 upward and downward in the load chamber 210. By this configuration, the carrier lift mechanism 222 may be configured to move the transport carrier 300 in a stepping movement synchronized with a pick up sequence of the substrate transfer mechanism 132. The transport carrier 300 is moved upward or downward in a pitch after one of the substrates 12 in the transport carrier 300 is picked up by the substrate transfer mechanism 132. And, the above step is repeated until all of the substrates 12 in the transport carrier 300 are picked up. Similarly, the processed substrates 12 can be loaded into the transport carrier 300 by reversing the above step.

Without additional load ports at sides of conventional equipment front end module (EFEM), the transport carrier 300 can be loaded into the sealed load chamber 210 directly through the load opening 212 at the top end 214 of the load chamber 210. Therefore, as compared with a conventional semiconductor processing station, the total footprint of the semiconductor processing station 10 is dramatically reduced, and tools of the semiconductor processing station 10 are less complicated so as to lower tool cost and increase tool throughput.

Referring to FIG. 2, in some embodiments, the semiconductor processing station 10 further comprises a carrier transport track 400 for transporting the transport carrier 300 outside the load chamber 210 and facilitates to load the transport carrier 300 into the load chamber 210. More specifically, the carrier transport track 400 has a top side 410 configured to load and move the transport carrier 300 and a bottom side 420 configured to drive the movable cover 230 to open the load chamber 210. Detailed operations of loading the transport carrier 300 accompanying with the carrier transport track 400 is further illustrated below.

FIG. 3 through FIG. 9 are schematic front views of the semiconductor processing station in FIG. 1 illustrating load process of the transport carrier according to some embodiments of the present disclosure.

At first, as shown in FIG. 3, the load chamber 210 comprises a first load chamber 210a and a second load chamber 210b. The carrier transport track 400 is disposed over the first load chamber 210a and the second load chamber 210b. An automated material handling system (AMHS) 500 is used to transport the transport carrier 300 to the carrier transport track 400. Herein, transport carriers 300a and 300b with processed substrates are respectively removed from the first load chamber 210a and the second load chamber 210b to the top side 410 of the carrier transport track 400. In some embodiments, the semiconductor processing station 10 further comprises one or more buffer ports, such as a first buffer port 600a and a second buffer port 600b, disposed at sides of the first load chamber 210a and the second load chamber 210b and configured to evacuate the transport carriers 300a and 300b with processes substrates. Transport carriers 300c and 300d with unprocessed substrates are respectively loaded to the first buffer port 600a and the second buffer port 600b by the AMHS 500.

Then, as shown in FIG. 4, the transport carrier 300d with unprocessed substrates is moved into a buffer space of the second buffer port 600b from the top side 410 to the bottom side 420 of the carrier transport track 400. Therefore, the space original occupied by the transport carrier 300d with unprocessed substrates at the top side 410 of the carrier transport track 400 is released.

Then, as shown in FIG. 5, the transport carrier 300c with unprocessed substrates and the transport carriers 300a and 300b with processed substrates are moved left by the carrier transport track 400. At this time, the movable cover 230a of the first load chamber 210a is removed by the bottom side 420 of the carrier transport track 400 to open the first load chamber 210a by for example electrical magnetic force or other applicable manners. The transport carrier 300c with unprocessed substrates now is corresponding to the first load chamber 210a.

Next, as shown in FIG. 6, the transport carrier 300c with unprocessed substrates is loaded into the first load chamber 210a. And, the movable cover 230a returns back to seal the first load chamber 210a.

Then, as shown in FIG. 7, the transport carriers 300a and 300b with processed substrates are moved right by the carrier transport track 400. The space original occupied by the transport carriers 300b with processed substrates at the top side 410 of the carrier transport track 400 is released. At this time, the movable cover 230b of the second load chamber 210b is removed by the bottom side 420 of the carrier transport track 400 to open the second load chamber 210b by for example electrical magnetic force or other applicable manners. And, the transport carrier 300d with unprocessed substrates in the buffer space of the second buffer port 600b at the bottom side 420 of the carrier transport track 400 is now moved back to the top side 410 of the carrier transport track 400.

Thereafter, as shown in FIG. 8, the transport carrier 300d with unprocessed substrates now can be loaded into the second load chamber 210b. And then, the movable cover 230b returns back to seal the second load chamber 210b.

After the above steps of FIG. 3 through FIG. 8, the transport carriers 300c and 300d with unprocessed substrates are completely loaded into the sealed first load chamber 210a and the sealed second load chamber 210b. Then, the unprocessed substrates can be transferred by mechanisms of the platform 100 and the load port 200 to the processing modules 120 as mentioned in FIG. 1 and FIG. 2, to perform manufacturing procedures on the unprocessed substrates. In addition, the transport carriers 300a and 300b with processed substrates can be picked up and transported by the AMHS 500 away from the semiconductor processing station 10.

Furthermore, as shown in FIG. 9, after the substrates of the transport carriers 300c and 300d are processed, the transport carriers 300c and 300d with processed substrates are respectively removed from the first load chamber 210a and the second load chamber 210b to the top side 410 of the carrier transport track 400. And, transport carriers 300e and 300f with unprocessed substrates are respectively loaded to the first buffer port 600a and the second buffer port 600b by the AMHS 500. The process now is returned to the status as shown in FIG. 3. An automated carrier loading and transporting process complying with the operations of the platform 100 and the load port 200 can be accomplished by repeating the steps as shown in FIG. 3 through FIG. 9.

Accompanying with FIG. 1 through FIG. 9, methods of operating the semiconductor processing station 10 as mentioned above is further illustrated below. Detailed descriptions of the relevant components or steps can be referred to the aforementioned embodiments, and will not be repeated hereinafter.

FIG. 10 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure. At first, a transport carrier 300 loaded into a load chamber 210 of the load port 200 through a load opening 212 at a top end 214 of a load chamber 210 (Step 1010). Then, the transport carrier 300 is transferred to an intake/outtake port 110 of a platform 100 (Step 1020). Next, a plurality of substrates 12 in the transport carrier 300 are picked up and traversely transferred from the transport carrier 300 to a plurality of processing modules 120 of the platform 100 in sequence (Step 1030). Then, a process is performed to the substrate 12 in each of the processing modules (Step 1040).

The processing modules 120 may be configured to perform any manufacturing procedure on the substrate 12. Substrate manufacturing procedures include deposition processes such as physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), plasma-enhanced chemical vapor deposition (“PECVD”), electrochemical deposition (“ECD”), molecular beam epitaxy (“MBE”), atomic layer deposition (“ALD”) and/or other deposition processes; etching processes including wet and dry etching and ion beam milling; lithographic exposure; ion implantation; thermal processes such as annealing and/or thermal oxidation; cleaning processes such as rinsing and/or plasma ashing; chemical mechanical polishing or chemical mechanical planarizing (collectively “CMP”) processes; testing; any procedure involved in the processing of the substrate 12; and/or any combination of procedures.

FIG. 11 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure. At first, a transport carrier 300 loaded into a load chamber 210 of the load port 200 through a load opening 212 at a top end 214 of a load chamber 210 (Step 1110). Then, the load chamber 210 may be sealed by a movable cover 230 and a vacuum environment can be formed in the load chamber 210 (Step 1120). Then, the transport carrier 300 is transferred to an intake/outtake port 110 of a platform 100 by, for example, a carrier transfer module 220 configured in the load chamber 210 (Step 1130). Next, a plurality of substrates 12 in the transport carrier 300 are picked up and traversely transferred from the transport carrier 300 to a plurality of processing modules 120 of the platform 100 in sequence by, for example, a substrate transfer mechanism 132 configured in a central transfer module 130 communicating with the intake/outtake port 110 and the plurality of processing modules 120 of the platform 100 (Step 1140). Then, a process as mentioned above is performed to the substrate 12 in each of the processing modules (Step 1150).

FIG. 12 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure. At first, a transport carrier 300 loaded into a load chamber 210 of the load port 200 through a load opening 212 at a top end 214 of a load chamber 210 (Step 1210). Then, the transport carrier 300 is transferred to an intake/outtake port 110 of a platform 100 by, for example, a carrier transfer module 220 configured in the load chamber 210 (Step 1220). Next, the transport carrier 300 may be moved upward and downward in the load chamber 210 in a stepping movement by the carrier transfer module 220 (Step 1230). And, at the same time, a plurality of substrates 12 in the transport carrier 300 are picked up and traversely transferred from the transport carrier 300 to a plurality of processing modules 120 of the platform 100 in sequence synchronized with the step movement of the transport carrier 300 by, for example, a substrate transfer mechanism 132 configured in a central transfer module 130 communicating with the intake/outtake port 110 and the plurality of processing modules 120 of the platform 100 (Step 1240). Then, a process as mentioned above is performed to the substrate 12 in each of the processing modules (Step 1250).

FIG. 13 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure. At first, a transport carrier 300 loaded into a load chamber 210 of the load port 200 through a load opening 212 at a top end 214 of a load chamber 210 (Step 1310). Then, the transport carrier 300 is transferred to an intake/outtake port 110 of a platform 100 (Step 1320). Next, a plurality of substrates 12 in the transport carrier 300 are picked up and traversely transferred from the transport carrier 300 to a plurality of processing modules 120 of the platform 100 in sequence (Step 1330). Then, a process as mentioned above is performed to the substrate 12 in each of the processing modules (Step 1340). Herein, the step 1310 of loading the transport carrier 300 into the load chamber 210 may be performed by a carrier transport track 400 having a top side 410 configured to load and move the transport carrier 300 and a bottom side 420 configured to open the load chamber 210. Then, the transport carrier 300 may be evacuated from the load chamber 210 to a buffer port 600a or 600b after the plurality of substrates 12 in the transport carrier 300 are processed (Step 1350). And, in Step 1350, the load chamber 210 may be opened as the transport carrier 300 is evacuated from the load chamber 210 to the buffer port 600a or 600b.

FIG. 14 is a flow chart showing the steps of a semiconductor process according to some embodiments of the present disclosure. At first, a transport carrier 300 loaded into a load chamber 210 of the load port 200 through a load opening 212 at a top end 214 of a load chamber 210 (Step 1410). Then, the load chamber 210 may be sealed by a movable cover 230 and a vacuum environment can be formed in the load chamber 210 (Step 1420). Then, the transport carrier 300 is transferred to an intake/outtake port 110 of a platform 100 by, for example, a carrier transfer module 220 configured in the load chamber 210 (Step 1430). Next, the transport carrier 300 may be moved upward and downward in the load chamber 210 in a stepping movement by the carrier transfer module 220 (Step 1440). And, at the same time, a plurality of substrates 12 in the transport carrier 300 are picked up and traversely transferred from the transport carrier 300 to a plurality of processing modules 120 of the platform 100 in sequence synchronized with the step movement of the transport carrier 300 by, for example, a substrate transfer mechanism 132 configured in a central transfer module 130 communicating with the intake/outtake port 110 and the plurality of processing modules 120 of the platform 100 (Step 1450). Then, a process as mentioned above is performed to the substrate 12 in each of the processing modules (Step 1460). Herein, the step 1310 of loading the transport carrier 300 into the load chamber 210 may be performed by a carrier transport track 400 having a top side 410 configured to load and move the transport carrier 300 and a bottom side 420 configured to open the load chamber 210. Then, the transport carrier 300 may be evacuated from the load chamber 210 to a buffer port 600a or 600b after the plurality of substrates 12 in the transport carrier 300 are processed (Step 1470). And, in Step 1470, the load chamber 210 may be opened as the transport carrier 300 is evacuated from the load chamber 210 to the buffer port 600a or 600b.

According to some embodiments, a semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

According to some embodiments, a semiconductor processing station includes a platform, a load port, and a carrier transport track. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber and a movable cover. The load chamber communicates with the intake/outtake port and has a load opening for receiving a transport carrier within the load chamber. The movable cover covers the load opening. The carrier transport track has a bottom side configured to open the load chamber.

According to some embodiments, a semiconductor processing station includes a platform and a load port. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber, the movable cover is disposed at the load opening and configured to seal the load opening, and the carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transfer module is configured to move the transport carrier upward and downward in the load chamber.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor processing station, comprising:

a platform comprising an intake/outtake port and a plurality of processing modules;
a load port comprising: a load chamber communicating with the intake/outtake port and having a load opening at its top end for receiving a transport carrier within the load chamber; a movable cover disposed at the load opening and configured to seal the load opening; and a carrier transfer module configured to transfer the transport carrier to the intake/outtake port; and
a carrier transport track having a bottom side configured to open the load chamber.

2. The semiconductor processing station of claim 1, wherein the load opening is sealed by the movable cover to form a vacuum environment containing the transport canier.

3. The semiconductor processing station of claim 1, wherein the platform further comprises:

a central transfer module communicating with the intake/outtake port and the plurality of processing modules; and
a substrate transfer mechanism configured in the central transfer module to pick up and traversely transfer a plurality of substrates from the transport carrier to the plurality of processing modules in sequence.

4. The semiconductor processing station of claim 3, wherein the carrier transfer module comprises a carrier lift mechanism configured to move the transport carrier upward and downward in the load chamber.

5. The semiconductor processing station of claim 4, wherein the carrier lift mechanism is configured to move the transport carrier in a stepping movement synchronized with a pick up sequence of the substrate transfer mechanism.

6. The semiconductor processing station of claim 1, wherein the carrier transport track has a top side configured to load and move the transport carrier and the bottom side of the carrier transport track is configured to drive the movable cover to open the load chamber.

7. The semiconductor processing station of claim 6, further comprising:

a buffer port disposed at a side of the load chamber and configured to evacuate the transport carrier.

8. A semiconductor processing station, comprising:

a platform comprising an intake/outtake port and a plurality of processing modules;
a load port comprising: a load chamber communicating with the intake/outtake port and having a load opening for receiving a transport carrier within the load chamber; and a movable cover covering the load opening; and
a carrier transport track having a bottom side configured to open the load chamber.

9. The semiconductor processing station of claim 8, wherein the load opening is covered and sealed by the movable cover to form a vacuum environment.

10. The semiconductor processing station of claim 8, wherein the platform further comprises:

a central transfer module communicating with the intake/outtake port and the plurality of processing modules; and
a substrate transfer mechanism configured in the central transfer module to pick up and traversely transfer a plurality of substrates from the transport carrier to the plurality of processing modules in sequence.

11. The semiconductor processing station of claim 8, further comprising:

a carrier transfer module configured to transfer the transport carrier to the intake/outtake port.

12. The semiconductor processing station of claim 11, wherein the carrier transfer module comprises a carrier lift mechanism configured to move the transport carrier upward and downward in the load chamber.

13. The semiconductor processing station of claim 12, wherein the carrier lift mechanism is configured to move the transport carrier in a stepping movement synchronized with a pick up sequence of the substrate transfer mechanism.

14. The semiconductor processing station of claim 8, wherein the carrier transport track has a top side configured to load and move the transport carrier and the bottom side of the carrier transport track is configured to drive the movable cover to reveal the load opening of the load chamber.

15. The semiconductor processing station of claim 6, further comprising:

a buffer port disposed at a side of the load chamber and configured to evacuate the transport carrier.

16. A semiconductor processing station, comprising:

a platform comprising an intake/outtake port and a plurality of processing modules; and
a load port comprising: a load chamber communicating with the intake/outtake port and having a load opening at its top end for receiving a transport carrier within the load chamber; a movable cover disposed at the load opening and configured to seal the load opening; and
a carrier transfer module configured to transfer the transport carrier to the intake/outtake port, the carrier transfer module being configured to move the transport carrier upward and downward in the load chamber.

17. The semiconductor processing station of claim 16, wherein the load opening is sealed by the movable cover to form a vacuum environment containing the transport carrier.

18. The semiconductor processing station of claim 16, wherein the platform further comprises:

a central transfer module communicating with the intake/outtake port and the plurality of processing modules; and
a substrate transfer mechanism configured in the central transfer module to pick up and traversely transfer a plurality of substrates from the transport carrier to the plurality of processing modules in sequence.

19. The semiconductor processing station of claim 16, wherein the carrier transport track has a top side configured to load and move the transport carrier and the bottom side of the carrier transport track is configured to drive the movable cover to open the load chamber.

20. The semiconductor processing station of claim 19, further comprising:

a buffer port disposed at a side of the load chamber and configured to evacuate the transport carrier.
Referenced Cited
U.S. Patent Documents
5752796 May 19, 1998 Muka
8851819 October 7, 2014 Kamikawa
20160035596 February 4, 2016 Kamiya
Patent History
Patent number: 10510572
Type: Grant
Filed: Jun 24, 2019
Date of Patent: Dec 17, 2019
Patent Publication Number: 20190311930
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsinchu)
Inventors: You-Hua Chou (Hsinchu), Chih-Wei Huang (Hsinchu), Kuo-Sheng Chuang (Hsinchu), Cheng-Chung Chien (Hsinchu)
Primary Examiner: Glenn F Myers
Application Number: 16/449,452
Classifications
Current U.S. Class: For Carrying Standarized Mechanical Interface (smif) Type (414/217.1)
International Classification: H01L 21/677 (20060101);