Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes an acoustic wave resonator (AWR) die. The RF FEM may further include an active die coupled with the package substrate of the RF FEM. When the active die is coupled with the package substrate, the AWR die may be between the active die and the package substrate. Other embodiments may be described or claimed.

Abstract: A BAW resonator comprises a bottom electrode, a piezoelectric layer and a top electrode. A top electrode connection is arranged in a plane above the top electrode. For doing this a spacer is arranged on the top electrode. A capping layer is sitting on the spacer distant from the top electrode such that an air-filled gap to the top electrode is kept. The top electrode connection can now be arranged above the capping layer. An electrically conductive path connects the top electrode and the top electrode connection. Such a resonator needs only one lateral design and can provide a low-ohmic interconnection of resonators e.g. in a filter circuit.

Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and having openings exposing the conductor pads, respectively, and plating bumps formed on the conductor pads such that each of the plating bumps includes a base plating layer formed in a respective one of the openings of the solder resist layer, and a top plating layer formed on the base plating layer. The plating bumps are formed such that the base plating layer has an upper surface and a side surface including a portion protruding from the solder resist layer and having a rough surface and that the top plating layer has a hemispherical shape and is covering only the upper surface of the base plating layer.

Abstract: A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

Abstract: A method for manufacturing a metal card includes: a step for forming a metal card by laminating a stack of sheets in which are stacked a plurality of sheets, centered on a metal sheet, including adhesive sheets having the same size as the metal sheet, an upper inlay sheet having a first antenna, and a lower inlay sheet having a second antenna; a step for forming a COB accommodation space, which can accommodate a COB, by milling a certain area of the metal card using computerized numerical control (CNC) machining; a step for forming a through-hole, which exposes the first antenna and the second antenna, by milling a COB contact point region of the COB accommodation space down to the lower inlay sheet; a step for electrically connecting the first antenna and the second antenna by dispensing a conductive elastic liquid into the through-hole; and a step for bidirectionally connecting the first antenna and the second antenna to the COB by attaching the COB within the COB accommodation space so that the COB contact

Abstract: Film bulk acoustic resonator (FBAR) is provided. An exemplary FBAR includes a substrate; a first insulating material layer on the substrate, the first insulating material layer containing a first cavity; a second insulating material layer on the first insulating material layer, the second insulating material layer containing a second cavity and a third cavity spaced apart from the second cavity, the second cavity and the third cavity both in communication with the first cavity; a resonator sheet covering the second cavity and partially extending over the second insulating material layer; a third insulating material layer over the second insulating material layer and the resonator sheet, the third insulating material layer containing a fourth cavity, the fourth cavity in communication with the third cavity, and the fourth cavity partially overlapping the second cavity; and a capping layer on the third insulating material layer.

Abstract: A wiring board includes a substrate and a plurality of monolithic ceramic capacitors connected in series on the substrate. The plurality of monolithic ceramic capacitors includes a first monolithic ceramic capacitor oriented in a first direction and a second monolithic ceramic capacitor oriented in a second direction. The second direction is at an angle of 45±5 degrees relative to the first direction.

Abstract: The invention relates to a DC link capacitor module (1, 1?), in which a coil (4, 5) is electrically conductively attached to two mutually opposite electrode plates (2a, 2b), wherein a plurality of first connecting means (6) are provided on each electrode plate (2a, 2b) to produce a detachable or non-detachable plug-in connection to second connecting means (9a, 9b), which correspond thereto and are attached to a bus bar (7a, 7b) of a power electronics module (8).

Abstract: In accordance with embodiments disclosed herein, there is provided a high-density dual-embedded-microstrip interconnect. An interconnect includes a reference layer and a dielectric disposed on the reference layer. The interconnect further includes a pair of conductors including a first conductor and a second conductor that are in an edge-facing orientation. The interconnect further includes a third conductor. The pair of conductors may be disposed within the dielectric and the third conductor may be disposed on the dielectric above the pair of conductors. The pair of conductors may be disposed on the dielectric and the third conductor may be disposed within the dielectric below the pair of conductors. First noise received by the third conductor from the first conductor and second noise received by the third conductor from the second conductor at least partially cancel out.

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

Abstract: An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

Abstract: An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.

Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.

Abstract: A system in package module assembly is provided, and includes: a substrate, and a chip, an inductor, and an electrical element that are electrically connected to the substrate. The substrate includes a first surface, a second surface opposite to the first surface, and an accommodation groove. The accommodation groove passes through the second surface and the first surface. The inductor includes a magnetic core and an inductive coil. The magnetic core includes a base and a protrusion disposed on an outer surface of the base. The outer surface on which the protrusion is disposed and that is of the base abuts on the second surface. The protrusion is accommodated in the accommodation groove. The inductive coil is disposed in the protrusion. A system in package module and an electronic device are further provided.

Abstract: An automated breadboard wiring assembly includes a breadboard with holes therein defining at least two nodes and at least a primary wiring board. The primary wiring board has a wiring matrix composed of a plurality of interconnected wiring segments, each wiring segment having a switch therealong. A plurality of contacts are interconnected with the wiring matrix with a switch positioned between each contact and the wiring matrix. Each contact is configured to engage a respective one of the breadboard nodes. An input device is configured to indicate desired wires between nodes and the locations of the desired wires define wiring information. A microprocessor configured to receive wiring information from the input device and open selective ones of the switches such that an electrical path along selective ones of the contacts and the wire segments is defined to correspond to each desired wire set forth in the wiring information.

Abstract: A power conversion circuit has a multilayer transformer and a plurality of rectifying transistors coupled to the secondary windings of the multilayer transformer. The multilayer transformer is formed as multiple layers within a PCB stack, where primary winding conductors and secondary winding conductors are vertically aligned and stacked. The secondary winding conductors are constructed to have one or more secondary winding arms that provide area to which the plurality of rectifying transistors are physically connected. The primary winding conductors are constructed to have a primary winding arm. A footprint of each primary winding conductor is configured to substantially overlap an entire footprint of each of the secondary winding conductors. As such, an entirety of the secondary current flowing through the secondary winding conductors is vertically aligned with the primary winding conductors, and therefore with the primary current flowing through the secondary winding conductors.

Abstract: A voltage regulator module includes a first circuit board assembly, a second circuit board assembly and a magnetic core assembly. The first circuit board assembly includes a first printed circuit board. The second circuit board assembly includes a second printed circuit board, at least one output capacitor, a plurality of ball grid arrays and at least one bonding pad. The second printed circuit board includes a first surface and a second surface. The plurality of ball grid arrays are disposed on the second surface of the second printed circuit board. The at least one bonding pad is arranged beside the first surface of the second printed circuit board. The magnetic core assembly is arranged between the first circuit board assembly and the second circuit board assembly and electrically connected with the at least one bonding pad. The at least one output capacitor is embedded within the second circuit board assembly.

Abstract: A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil.

Abstract: A first board includes a first ground plane, a first ground land, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are formed on the same surface. A second board includes a second ground plane, a second ground land, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are formed on a surface opposing the first board. The second ground land and the second signal land oppose the first ground land and the first signal land, respectively. A conduction member connects the first ground land and the second ground land. The first signal land and the second signal land are connected by capacitance coupling without using any conductor.

Abstract: An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion.

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

Abstract: A technique for tuning a ladder-shaped inductor that achieves a finer tuning resolution by severing one or more shorts, skipping the severing of one or more shorts, and severing one or more subsequent shorts within the ladder-shaped inductor. This technique can be applied to a voltage-controlled oscillator using a differential or single-ended ladder-shaped inductor as part of the resonant circuit. Within an oscillator, such a technique provides for a more precise modulation of the effective inductance of the ladder-shaped inductor, which enables an improved tuning resolution of the operating frequency of the oscillator.

Abstract: Provided is a contactor disposed on a conductor coming into contact with a user of an electronic device and an internal circuit. The contactor includes a contact part and an electric shock prevention part, which are disposed to face each other, and, of which at least portions respectively come into contact with the conductor and the internal circuit, wherein the electric shock prevention part includes a laminate in which a plurality of insulation sheets are vertically laminated between the internal circuit and the conductor and an external electrode disposed on a side surface of the laminate, and at least one portion of the external electrode extends to one surface of the laminate and is connected to a ground terminal or the conductor, and at least the other portion extends to the other surface of the laminate to come into contact with the contact part.

Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.

Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.

Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.

Abstract: According to an embodiment, a wireless device includes an interposer, a semiconductor chip, electrodes, and a slot antenna. The interposer includes conductive layers disposed at least at a side of a component mounting surface and a side of a reverse surface opposite to the component mounting surface. The semiconductor chip is mounted on the component mounting surface and includes a built-in transceiving circuit. The electrodes are disposed in a conductive layer disposed at the side of the reverse surface of the interposer so as to be electrically connected to an outside of the wireless device. At least a portion of the slot antenna is disposed in at least one of the conductive layers of the interposer. A shortest distance between an end in a width direction of the slot antenna and the electrodes is smaller than a sum of a minimum line width and a minimum line space of the interposer.

Abstract: A rigid flex circuit comprised of high thermal conductivity sections, said sections having components disposed so as to have their contacts substantially planar with the surface of the thermally conductive section and wherein the contacts are interconnected directly to the traces without the use of solder and further having the thermally conductive sections interconnected to one another by means of flexible circuit sections.

Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.

Abstract: A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.

Abstract: A power supply converter and a method for manufacturing the same are provided. The power supply converter includes an inductance component and a power component, wherein the inductance component includes: a first magnetic substrate, provided with a first via, the first magnetic substrate including a first surface and a second surface, and a first pin being provided on the first surface; a second magnetic substrate, provided with a second via, and having a second surface provided with a second pin; an inductance coil, provided between the first surface and the second surface and having a first end and a second end formed at the vias and connected to the first and second pin, respectively; and a filling part, at least partly filling the vias, wherein the power component and the inductance component are stacked, are in contact and are coupled to each other.

Abstract: A power tube connection structure includes a substrate, a printed circuit board, and a power tube, where a through groove allowing the power tube to pass through is cut into the printed circuit board, a mounting groove is cut into the upper surface of the substrate at a location corresponding to the through groove, one end of the power tube extends through the through groove, and is welded onto a bottom face of the mounting groove, the end of the power tube that extends into the mounting groove abuts onto a side wall of the mounting groove close to an output end of the power amplifier, and a solder flux escape channel is made into the side wall of the mounting groove close to the output end of the power amplifier.

Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.

Abstract: The invention relates to a patch antenna. The invention also relates to an antenna system for transmitting and receiving electromagnetic signals comprising at least one antenna according to the invention. The invention further relates to a method of manufacturing an antenna according to the invention. The invention moreover relates to a method for use in wireless communications by using an antenna according to the invention. The invention additionally relates to a RF transceiver of a wireless communications device comprising at least one antenna according to the invention. The invention further relates to an electronic device comprising an RF transceiver according to the invention.

Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.

Abstract: A multilayer ceramic capacitor is configured such that “a” is a distance in a height direction between an effective portion and a first principal surface; “b” is a distance in a length direction between a first end surface and the effective portion in the length direction; “c” is a thickness of the thickest portion of a first base layer provided over the first principal surface; “d” is a distance in the length direction between the thickest portion of the first base layer provided over the first end surface and a portion of the first base layer located over the first principal surface and closest to a second end surface; and “e” is a maximum thickness of a portion of the first base layer provided over the first end surface; and f: the height of the ceramic body, and 2?(c·d+e·f/2)/(a·b)?6 is satisfied.

Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.

Abstract: An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core layers. The buildup layers have a top side that includes first and second surface features for receiving the voltage regulator and the load, respectively. First and second pluralities of vias connect the first and second surface features, respectively, to a buildup conductor layer and a core conductor layer. The buildup conductor layer includes a substantially solid or continuous conductor plane extending across and connected to the first and second pluralities of vias. The buildup conductor layer defines a gap between the first and second pluralities of vias, the gap partially separating a portion of the conductor plane connected to the first plurality of vias from a portion connected to the second plurality of vias.

Abstract: Bypass techniques are provided herein to protect noise sensitive circuits from both internal and external noise sources. According to one embodiment, an integrated circuit (IC) chip may include a noise sensitive circuit coupled between a power supply pad and a first ground pad of the IC chip. In order to protect the first ground pad of the noise sensitive circuit, two distinct bypass paths are provided to route noise current around the noise sensitive circuit. Each bypass path terminates in its own ground pad (e.g., a second ground pad and third ground pad), which is separate from the first ground pad of the noise sensitive circuit.

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.

Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.

Abstract: Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation.

Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.

Abstract: A power module is disclosed. The power module includes a magnetic assembly, a switching device, a first upper conductive element and a first sidewall conductive element. The magnetic assembly has a first magnetic core, a second magnetic core and a receiving space. The first magnetic core has a first top surface, a first bottom surface and at least one first sidewall through-hole. The second magnetic core is coupled with the first magnetic core. The receiving space is formed between the first magnetic core and the second magnetic core. The switching device is disposed on the first top surface and accommodated in the receiving space. The first upper conductive element is disposed on the first top surface of the first magnetic core and electrically connected to the switch component. The first sidewall conductive element is disposed in the first sidewall through-hole and electrically connected to the first upper conductive element.

Abstract: Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.

Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1> about 0.15 and a condition of t3/t1> about 0.15 are satisfied.

Abstract: In a three phase inverter device, a smoothing capacitor, a bus bar at a positive electrode side and a bus bar at a negative electrode side are formed on a first surface of the circuit substrate. Electronic components containing a microcomputer, etc., a differential wiring pattern, a single wiring pattern and a current wiring pattern are formed on a second surface of the circuit substrate. A ground pattern is formed in the inside of the circuit substrate in order to separate the electronic components, the differential wiring pattern, the single wiring pattern and the current wiring pattern from the smoothing capacitor, the bus bar at the positive electrode side and the bus bar at the negative electrode side.