Having Passive Component Patents (Class 361/782)
  • Patent number: 10777514
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Patent number: 10763782
    Abstract: A technique for tuning a ladder-shaped inductor that achieves a finer tuning resolution by severing one or more shorts, skipping the severing of one or more shorts, and severing one or more subsequent shorts within the ladder-shaped inductor. This technique can be applied to a voltage-controlled oscillator using a differential or single-ended ladder-shaped inductor as part of the resonant circuit. Within an oscillator, such a technique provides for a more precise modulation of the effective inductance of the ladder-shaped inductor, which enables an improved tuning resolution of the operating frequency of the oscillator.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 1, 2020
    Assignee: NXP USA, INC.
    Inventors: Kun-Hin To, David Gareth Morgan, Jay Paul John, James Albert Kirchgessner
  • Patent number: 10716196
    Abstract: Provided is a contactor disposed on a conductor coming into contact with a user of an electronic device and an internal circuit. The contactor includes a contact part and an electric shock prevention part, which are disposed to face each other, and, of which at least portions respectively come into contact with the conductor and the internal circuit, wherein the electric shock prevention part includes a laminate in which a plurality of insulation sheets are vertically laminated between the internal circuit and the conductor and an external electrode disposed on a side surface of the laminate, and at least one portion of the external electrode extends to one surface of the laminate and is connected to a ground terminal or the conductor, and at least the other portion extends to the other surface of the laminate to come into contact with the contact part.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 14, 2020
    Assignee: MODA-INNOCHIPS CO., LTD.
    Inventors: Seung Hun Cho, Sung Jin Heo, Dong Suk Lee
  • Patent number: 10568199
    Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
  • Patent number: 10568198
    Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: February 18, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
  • Patent number: 10568200
    Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
  • Patent number: 10553954
    Abstract: According to an embodiment, a wireless device includes an interposer, a semiconductor chip, electrodes, and a slot antenna. The interposer includes conductive layers disposed at least at a side of a component mounting surface and a side of a reverse surface opposite to the component mounting surface. The semiconductor chip is mounted on the component mounting surface and includes a built-in transceiving circuit. The electrodes are disposed in a conductive layer disposed at the side of the reverse surface of the interposer so as to be electrically connected to an outside of the wireless device. At least a portion of the slot antenna is disposed in at least one of the conductive layers of the interposer. A shortest distance between an end in a width direction of the slot antenna and the electrodes is smaller than a sum of a minimum line width and a minimum line space of the interposer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 4, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Makoto Sano, Koh Hashimoto, Makoto Higaki
  • Patent number: 10517174
    Abstract: A rigid flex circuit comprised of high thermal conductivity sections, said sections having components disposed so as to have their contacts substantially planar with the surface of the thermally conductive section and wherein the contacts are interconnected directly to the traces without the use of solder and further having the thermally conductive sections interconnected to one another by means of flexible circuit sections.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 24, 2019
    Inventor: Joseph Charles Fjelstad
  • Patent number: 10483249
    Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Edward A. Burton, Gerhard Schrom, Larry E. Mosley
  • Patent number: 10433425
    Abstract: A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Kai Liu, Changhan Hobie Yun, Jonghae Kim, Mario Francisco Velez
  • Patent number: 10389241
    Abstract: A power supply converter and a method for manufacturing the same are provided. The power supply converter includes an inductance component and a power component, wherein the inductance component includes: a first magnetic substrate, provided with a first via, the first magnetic substrate including a first surface and a second surface, and a first pin being provided on the first surface; a second magnetic substrate, provided with a second via, and having a second surface provided with a second pin; an inductance coil, provided between the first surface and the second surface and having a first end and a second end formed at the vias and connected to the first and second pin, respectively; and a filling part, at least partly filling the vias, wherein the power component and the inductance component are stacked, are in contact and are coupled to each other.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: August 20, 2019
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Jianhong Zeng, Yu Zhang, Min Zhou, Jinping Zhou
  • Patent number: 10165675
    Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 25, 2018
    Assignee: American Technical Ceramics Corp.
    Inventor: John Mruz
  • Patent number: 10165687
    Abstract: A power tube connection structure includes a substrate, a printed circuit board, and a power tube, where a through groove allowing the power tube to pass through is cut into the printed circuit board, a mounting groove is cut into the upper surface of the substrate at a location corresponding to the through groove, one end of the power tube extends through the through groove, and is welded onto a bottom face of the mounting groove, the end of the power tube that extends into the mounting groove abuts onto a side wall of the mounting groove close to an output end of the power amplifier, and a solder flux escape channel is made into the side wall of the mounting groove close to the output end of the power amplifier.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Songlin Li, Pengbo Tian, Qingyun Wang, Liang Xu
  • Patent number: 10128572
    Abstract: The invention relates to a patch antenna. The invention also relates to an antenna system for transmitting and receiving electromagnetic signals comprising at least one antenna according to the invention. The invention further relates to a method of manufacturing an antenna according to the invention. The invention moreover relates to a method for use in wireless communications by using an antenna according to the invention. The invention additionally relates to a RF transceiver of a wireless communications device comprising at least one antenna according to the invention. The invention further relates to an electronic device comprising an RF transceiver according to the invention.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 13, 2018
    Assignee: The Antenna Company International N.V.
    Inventors: Diego Caratelli, Johan Leo Alfons Gielis, Vasiliki Paraforou, Luciano Mescia, Pietro Bia
  • Patent number: 10115526
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 30, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tadateru Yamada
  • Patent number: 10008330
    Abstract: A multilayer ceramic capacitor is configured such that “a” is a distance in a height direction between an effective portion and a first principal surface; “b” is a distance in a length direction between a first end surface and the effective portion in the length direction; “c” is a thickness of the thickest portion of a first base layer provided over the first principal surface; “d” is a distance in the length direction between the thickest portion of the first base layer provided over the first end surface and a portion of the first base layer located over the first principal surface and closest to a second end surface; and “e” is a maximum thickness of a portion of the first base layer provided over the first end surface; and f: the height of the ceramic body, and 2?(c·d+e·f/2)/(a·b)?6 is satisfied.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 26, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hiroto Itamura
  • Patent number: 9984829
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: May 29, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tadateru Yamada
  • Patent number: 9966345
    Abstract: An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core layers. The buildup layers have a top side that includes first and second surface features for receiving the voltage regulator and the load, respectively. First and second pluralities of vias connect the first and second surface features, respectively, to a buildup conductor layer and a core conductor layer. The buildup conductor layer includes a substantially solid or continuous conductor plane extending across and connected to the first and second pluralities of vias. The buildup conductor layer defines a gap between the first and second pluralities of vias, the gap partially separating a portion of the conductor plane connected to the first plurality of vias from a portion connected to the second plurality of vias.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 8, 2018
    Assignee: Google LLC
    Inventors: Gregory Sizikov, Woon Seong Kwon
  • Patent number: 9960756
    Abstract: Bypass techniques are provided herein to protect noise sensitive circuits from both internal and external noise sources. According to one embodiment, an integrated circuit (IC) chip may include a noise sensitive circuit coupled between a power supply pad and a first ground pad of the IC chip. In order to protect the first ground pad of the noise sensitive circuit, two distinct bypass paths are provided to route noise current around the noise sensitive circuit. Each bypass path terminates in its own ground pad (e.g., a second ground pad and third ground pad), which is separate from the first ground pad of the noise sensitive circuit.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 1, 2018
    Assignee: Silicon Laboratories Inc.
    Inventor: Navin Harwalkar
  • Patent number: 9921640
    Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Uwe Zillmann, Andre Schaefer, Ruchir Saraswat, Telesphor Kamgaing, Paul B. Fischer, Guido Droege
  • Patent number: 9854665
    Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: December 26, 2017
    Assignee: American Technical Ceramics Corp.
    Inventor: John Mruz
  • Patent number: 9759741
    Abstract: Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sooyong Park, Yong chul Jang, Kijae Song
  • Patent number: 9754722
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1>about 0.15 and a condition of t3/t1>about 0.15 are satisfied.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 5, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tadateru Yamada
  • Patent number: 9620448
    Abstract: A power module is disclosed. The power module includes a magnetic assembly, a switching device, a first upper conductive element and a first sidewall conductive element. The magnetic assembly has a first magnetic core, a second magnetic core and a receiving space. The first magnetic core has a first top surface, a first bottom surface and at least one first sidewall through-hole. The second magnetic core is coupled with the first magnetic core. The receiving space is formed between the first magnetic core and the second magnetic core. The switching device is disposed on the first top surface and accommodated in the receiving space. The first upper conductive element is disposed on the first top surface of the first magnetic core and electrically connected to the switch component. The first sidewall conductive element is disposed in the first sidewall through-hole and electrically connected to the first upper conductive element.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 11, 2017
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Jianhong Zeng, Shouyu Hong, Min Zhou
  • Patent number: 9607935
    Abstract: Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: March 28, 2017
    Assignee: ATI Technologies ULC
    Inventors: Liane Martinez, Neil McLellan, Silqun Leung, Gabriel Wong
  • Patent number: 9576727
    Abstract: In a capacitor main body, a dimension along the thickness direction of a first region where a first inner electrode and a second inner electrode are provided is t1, a dimension along the thickness direction of a second region that is positioned on the side of a first main surface relative to the first region is t2, and a dimension along the thickness direction of a third region that is positioned on the side of a second main surface relative to the first region is t3. A condition of t2/t1> about 0.15 and a condition of t3/t1> about 0.15 are satisfied.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 21, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tadateru Yamada
  • Patent number: 9401671
    Abstract: In a three phase inverter device, a smoothing capacitor, a bus bar at a positive electrode side and a bus bar at a negative electrode side are formed on a first surface of the circuit substrate. Electronic components containing a microcomputer, etc., a differential wiring pattern, a single wiring pattern and a current wiring pattern are formed on a second surface of the circuit substrate. A ground pattern is formed in the inside of the circuit substrate in order to separate the electronic components, the differential wiring pattern, the single wiring pattern and the current wiring pattern from the smoothing capacitor, the bus bar at the positive electrode side and the bus bar at the negative electrode side.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: July 26, 2016
    Assignee: DENSO CORPORATION
    Inventors: Jyunji Miyachi, Tsuneo Maebara, Yousuke Asako
  • Patent number: 9331030
    Abstract: An integrated antenna package including a laminated structure and a multi-layered substrate is provided. The laminated structure includes at least a chip embedded therein and at least a plated through-hole structure penetrating the laminated structure. The multi-layered substrate is stacked on the laminated structure. The multi-layered substrate includes at least a metal layer located on one side of the multi-layered substrate away from the laminated structure and the metal layer includes at least an antenna pattern located above the chip. The multi-layered substrate includes at least a plated via and through-hole structure penetrating the multi-layered substrate and electrically connected to the chip, so that the antenna pattern is electrically connect with the chip. Also, the manufacturing method of the integrated antenna package is provided.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: May 3, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Hua Tsai, Shyh-Jong Chung
  • Patent number: 9331004
    Abstract: An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within the encapsulation. The lead frame includes a first conductor forming a first conductive loop. A second conductor is galvanically isolated from the first conductor. The second conductor forms a second conductive loop proximate to and magnetically coupled to the first conductive loop to provide a magnetic communication link between the first and second conductors. A signal that is transmitted from a transmit circuit coupled to the first conductor is coupled to be received through the magnetic communication link by a receive circuit coupled to the second conductor.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 3, 2016
    Assignee: Power Integrations, Inc.
    Inventors: Balu Balakrishnan, David Michael Hugh Matthews
  • Patent number: 9299665
    Abstract: A structure fabrication method. An integrated circuit that includes N chip electric pads is bonded to a top side of an interposing shield that includes N electric conductors. N is at least 2. The interposing shield includes a shield material that includes a first semiconductor material. A bottom side of the interposing shield is polished, which exposes the N electric conductors to a surrounding ambient. The bonding includes bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors. The shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient. The polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Paul S. Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
  • Patent number: 9185804
    Abstract: A printed circuit board includes a first semiconductor package on a first surface layer of a printed wiring board and a second semiconductor package on a second surface layer where a bus signal is transmitted from the first to the second semiconductor package. A first bus wiring path from a signal terminal on an inner circumference side of the first semiconductor package via a via hole and the second surface layer to a signal terminal on an outer circumference side of the second semiconductor package and a second bus wiring path from a signal terminal on an outer circumference side of the first semiconductor package via the second surface layer and a via hole to a signal terminal on an inner circumference side of the second semiconductor package are provided, thus securing a return current path for a signal current and realizing a high density wiring while suppressing radiation noise.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: November 10, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Isono
  • Patent number: 9147664
    Abstract: A semiconductor package is provided. The semiconductor package includes a substrate, a first pad, a second, a first conductive element, a surface mount device, a first bonding wire and a molding compound layer. The first pad, the second pad, and the first conductive element are formed on the substrate. The surface mount device is mounted on the first pad and the second pad. The first bonding wire electrically connects the first conductive element and the first pad. The molding compound layer encapsulates the substrate, the first pad, the second pad, the first conductive element, the bonding wire and the surface mount device.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: September 29, 2015
    Assignee: MEDIATEK INC.
    Inventor: Nan-Jang Chen
  • Patent number: 9125301
    Abstract: A multilayer printed circuit board has an embedded heater layer having at least one elongated heater element trace of copper which is densely arranged in a predetermined circuitous path over at least part of the area of the board. The heater element has inputs configured for connection to a standard high current, low voltage power supply, and may also have ground connections for selective connection to a ground layer. The heater layer may be embedded in a carrier board of a surface mount module close to the lower solder interface layer, or may be embedded in a host board of an electronics assembly close to the mounting surface.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: September 1, 2015
    Assignee: Integrated Microwave Corporation
    Inventor: Jeffrey Sloane
  • Patent number: 9093313
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Patent number: 9042117
    Abstract: A semiconductor device effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichiro Hijioka, Akira Tanabe, Yoshihiro Hayashi
  • Patent number: 9042114
    Abstract: An electronic component includes an interposer, and a multilayer ceramic capacitor. The interposer includes a substrate including front and back surfaces that are parallel or substantially parallel to each other. Two first mounting electrodes and two second mounting electrodes are located on the front surface of the substrate, on opposite end portions in the longitudinal direction. Recesses are located in the longitudinal side surface of the insulating substrate. Connecting conductors are each provided in the side wall surface of each of the recesses. The connecting conductors connect a first external connection electrode and a second external connection electrode that are located on the back surface of the substrate, and first mounting electrodes and second mounting electrodes.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: May 26, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto
  • Publication number: 20150138744
    Abstract: A printed circuit board includes a baseboard, first and second conductive wires, a fuse, a 5V connector, a USB connector, and a CPU. The 5V connector is electrically connected to a first end of the fuse through the first conductive wire, and electrically connected to a voltage pin of the CPU voltage regulating chip through the second conductive wire. A voltage pin of the USB connector is connected to a second end of the fuse. The 5V connector outputs a 5V system voltage to the USB connector through the first conductive wire and the fuse, thus providing a voltage to a USB device, and also outputs the 5V system voltage to the CPU voltage regulating chip through the second conductive wire, thus signaling the CPU voltage regulating chip to convert the 5V system voltage and provide the converted voltage to a CPU.
    Type: Application
    Filed: April 11, 2014
    Publication date: May 21, 2015
    Applicants: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: SHI-PIAO LUO, SHENG-CUN ZHENG, CHIA-NAN PAI, SHOU-KUO HSU
  • Patent number: 9035194
    Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: M D Altaf Hossain, Jin Zhao, John T. Vu
  • Publication number: 20150131196
    Abstract: A multilayer ceramic capacitor may include: a ceramic body including dielectric layers, first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; a capacitor part including first internal electrodes and second internal electrodes; a resistor part including first internal connection conductors and second internal connection conductors; first dummy electrodes and second dummy electrodes; first to fourth external electrodes electrically connected to the first and second internal electrodes and the first and second internal connection conductors; and a first connection terminal and a second connection terminal. The capacitor part and the resistor part are connected in series to each other.
    Type: Application
    Filed: April 21, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min Cheol PARK, Sang Soo PARK
  • Publication number: 20150131194
    Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including a plurality of dielectric layers; a capacitor part including first and second internal electrodes formed in the ceramic body; a resistor part including a first internal connection conductor, a third internal connection conductor formed on one dielectric layer in the ceramic body and a second internal connection conductor, a fourth internal connection conductor formed on another dielectric layer in the ceramic body; first to fourth external electrodes formed on first and second main surfaces of the ceramic body; and a first connection terminal formed on first end surface of the ceramic body and a second connection terminal formed on second end surface of the ceramic body, wherein the capacitor part and the resistor part are connected to each other in series.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min Cheol PARK, Sang Soo PARK
  • Publication number: 20150131252
    Abstract: A multilayer ceramic electronic component may include: a multilayer ceramic capacitor including a ceramic body, a plurality of first and second internal electrodes formed to be alternately exposed to both side surfaces of the ceramic body, having a dielectric layer therebetween, and first and second external electrodes connected to the first and second internal electrodes, respectively; and an interposer board including an insulation board coupled to the mounting surface of the multilayer ceramic capacitor and first and second connection terminals formed on the insulation board and connected to the first and second external electrodes, respectively.
    Type: Application
    Filed: March 6, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Soo PARK, Min Cheol PARK
  • Publication number: 20150131199
    Abstract: A multilayer ceramic electronic component may include a ceramic body having a plurality of dielectric layers stacked in the ceramic body; a plurality of active layers including first and second internal electrodes disposed to be alternately exposed to the end surfaces of the ceramic body with the dielectric layers interposed between the first and second internal electrodes; and dummy layers disposed between the active layers.
    Type: Application
    Filed: April 23, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil PARK, Doo Young KIM, Young Ghyu AHN
  • Publication number: 20150131195
    Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers and having first and second main surfaces, first and second side surfaces, and first and second end surfaces; a capacitor part formed in the ceramic body and including first and second internal electrodes, the first internal electrode having a first lead exposed to the second main surface and the second internal electrode having a second lead exposed to the first main surface; resistor parts including first and second internal connection conductors formed on the same dielectric layers among the plurality of dielectric layers in the ceramic body; and first to fourth external electrodes, first and third connection terminals, and second and fourth connection terminals. The capacitor part and the resistor parts may be connected in series to one another.
    Type: Application
    Filed: April 2, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min Cheol PARK, Sang Soo PARK
  • Publication number: 20150131253
    Abstract: A multilayer ceramic electronic component may include: a multilayer ceramic capacitor including a ceramic body in which a plurality of dielectric layers are stacked, a pair of first external electrodes and a pair of second external electrodes formed on both side surfaces of the ceramic body and extended to portions of a mounting surface of the ceramic body, and first and second internal electrodes alternately stacked, having the dielectric layer therebetween, exposed through at least one side surface of the ceramic body, and connected to the first and second external electrodes, respectively; and an interposer substrate including an insulation substrate bonded to the mounting surface of the multilayer ceramic capacitor, and first and second connection terminals formed on the insulation substrate and connected to the first and second external electrodes, respectively.
    Type: Application
    Filed: April 8, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Soo Park, Min Cheol Park
  • Patent number: 9030836
    Abstract: An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-soo Park, Kyung-suk Kim
  • Publication number: 20150116973
    Abstract: The present invention discloses an electronic package structure. The body has a top surface with a cavity thereon, the first conductive element is disposed in the cavity, and the second conductive element is disposed in the body. The first external electrode electrically connected to the first conductive element and the second external electrode electrically connected to the second conductive element are both disposed on the top surface of the body or a first surface formed by the top surface of the encapsulation compound and the exposed portions of the top surface of the body which are not covered by the encapsulation compound.
    Type: Application
    Filed: January 10, 2015
    Publication date: April 30, 2015
    Inventors: DA-JUNG CHEN, Chun-Tiao Liu, BAU-RU LU
  • Publication number: 20150116892
    Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a capacitor part including a first internal electrode formed in the ceramic body and a second internal electrode formed in the ceramic body; a resistor part including a first internal connection conductor formed in the ceramic body and a second internal connection conductor formed in the ceramic body; a first dummy electrode formed in the ceramic body and a second dummy electrode formed in the ceramic body; and first to sixth external electrodes and the first and second internal connection conductors. The capacitor part and the resistor part may be connected in series to each other.
    Type: Application
    Filed: April 21, 2014
    Publication date: April 30, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min Cheol PARK, Sang Soo PARK
  • Publication number: 20150116972
    Abstract: A DC-DC converter assembly includes a board having a first side and a second side opposite the first side, a power stage die of a DC-DC converter attached to the first side of the board, and an output inductor electrically connected to an output of the power stage die and disposed over the power stage die on the first side of the board. The output inductor includes a magnetic core and an electrical conductor having first and second terminals attached to the first side of the board. The output inductor accommodates the power stage die under the magnetic core so that the power stage die is interposed between the magnetic core and the board. A corresponding method of manufacturing the DC-DC converter assembly and method of manufacturing the output inductor are also disclosed.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Inventors: Emil Todorov, Brian Molloy
  • Patent number: 9019717
    Abstract: A device having an integrated circuit and a circuit package. A first terminal contact, a second terminal contact, and a third terminal contact are brought out of the circuit package. The first terminal contact and the second terminal contact are each connected to terminals of the integrated circuit for power supply. The third terminal contact is connected to a terminal of the integrated circuit in the circuit package for signal transmission. A first capacitor is connected to the first terminal contact and a second capacitor is connected to the third terminal contact, wherein a fourth terminal contact and a fifth terminal contact are brought out of the circuit package, and the first capacitor is connected to the fourth terminal contact, and the second capacitor is connected to the fifth terminal contact.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 28, 2015
    Assignee: Micronas GmbH
    Inventor: Gerd Scholten
  • Publication number: 20150109750
    Abstract: An electronic system includes a printed circuit board (PCB), and a heat dissipating element. The PCB includes one or more first electronic components mounted on a first side of the PCB, and one or more second electronic components mounted on a second side of the PCB. The first electronic components have a power consumption that is greater than a threshold and have a height over the first side of the PCB that is higher than any other electronic components mounted on the first side of the PCB. At least one of the second electronic components has a height over the second side of the PCB that is higher than the height of the first electronic components. The heat dissipating element is adjacent to the first electronic components so as to provide a thermal coupling for dissipating heat generated by the first electronic components.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 23, 2015
    Applicant: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Daniel ELKASLASSY, Daniel KALMANOVIZ