SEMICONDUCTOR PACKAGE COMPRISING ALIGNMENT MEMBERS
A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.
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This application claims priority to Korean Patent Application No. 10-2006-0092455, filed on Sep. 22, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
Embodiments of the invention relate to a semiconductor package. In particular, embodiments of the invention relate to a semiconductor package comprising a semiconductor die and a tape substrate and further comprising an alignment member disposed on the semiconductor die and an alignment member disposed on the tape substrate.
2. Description of the Related Art
In an effort to make electronic devices such as portable personal computers and mobile phones lighter and more compact, there is an effort to make semiconductor devices used in those electronic devices smaller and able to perform multiple functions. One method for mounting such a semiconductor device (i.e., a semiconductor die) is to mount the semiconductor die using a flexible tape substrate such as a tape automated bonding (TAB) tape substrate. In the mounting method using the TAB tape substrate, inner leads disposed on a base film and bumps disposed on the semiconductor die are bonded to one another.
In the TAB tape substrate, wiring patterns are formed on the base film as in a chip on film (COF), and inner leads that are to be electrically connected to the wiring patterns are disposed on the base film. Bumps disposed on a semiconductor die are disposed corresponding to the inner leads disposed on the tape substrate, and the bumps are pressed to the inner leads by a pressing apparatus in order to electrically connect the inner leads and the bumps. In a semiconductor package using a conventional TAB tape substrate, in order to precisely connect the inner leads of the tape substrate and the bumps of the semiconductor die, the TAB tape substrate and the semiconductor die must be accurately aligned.
Conventionally, alignment keys for aligning the semiconductor die and the tape substrate were disposed on the semiconductor die and the tape substrate. Thus, the semiconductor die and the tape substrate were precisely aligned using the alignment keys, and the inner leads and the bumps were heated and pressed to connect to one another in an aligned state (i.e., after the semiconductor die and the tape substrate were aligned). Although a semiconductor die can be attached to the tape substrate by die attach equipment when using alignment keys, the tape substrate is deformed due to heat and pressure present during die attachment (i.e., while attaching the semiconductor die and the tape substrate) and misalignment between the tape substrate and the semiconductor die may occur. In particular, a semiconductor package having a relatively fine pitch and a relatively small allowance for deformation may suffer more from such misalignment, which may reduce the accuracy in the assembly of a semiconductor package.
SUMMARY OF THE INVENTIONEmbodiments of the invention provide a semiconductor package in which a semiconductor die and a tape substrate may be fixed to one another with more precise alignment.
In one embodiment, the invention provides a semiconductor package comprising a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further comprises a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.
In another embodiment, the invention provides a semiconductor package comprising a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further comprises a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate, wherein at least a portion of the first alignment member is disposed between portions of the second alignment member.
In yet another embodiment, the invention provides a semiconductor package comprising a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further comprises a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate, wherein at least a portion of the second alignment member is disposed between portions of the first alignment member.
Embodiments of the invention will be described herein with reference to the accompanying drawings, in which:
In the drawings, configurations or the like of some elements are intentionally exaggerated for clarity of description. Also, in the drawings, like reference symbols indicate like or similar elements.
Referring to
Semiconductor die 210 is mounted on a die mounting area of substrate portion 110. First connection terminals 220 are disposed on the upper surface of semiconductor die 210 and are disposed corresponding to second connection terminals 120 of tape substrate 110a. First connection terminals 220 comprise a plurality of first bumps 221 disposed along the first long side of semiconductor die 210 and disposed corresponding to first inner leads 121 of second connection terminals 120, and a plurality of second bumps 222 disposed along the first short side of semiconductor die 210 and disposed corresponding to second inner leads 122 of second connection terminals 120. Although it is not shown in the drawings, semiconductor die 210, first connection terminals 220, and second connection terminals 120 can be protected from elements disposed outside of semiconductor package 100a (i.e., protected from the outside) by an insulating material.
Semiconductor package 100a further comprises a first alignment member 231 disposed on semiconductor die 210, and a second alignment member 131 disposed on tape substrate 110a and disposed corresponding to first alignment member 231. In the embodiment illustrated in
The dummy bump of first alignment member 231 may have substantially the same shape as each of first and second bumps 221 and 222, and each of dummy inner leads 131a and 131b of second alignment member 131 may have substantially the same shape as each of first and second inner leads 121 and 122. First alignment member 231 may be disposed in a center portion of semiconductor die 210 or between two of second bumps 221 disposed along the first short side of semiconductor die 210. In addition, at least one more first alignment member 231 may be disposed between two of first bumps 221, between two of second bumps 222, in the center portion of semiconductor die 210, and/or at a similar position.
Alignment keys 240 and 140 are disposed on semiconductor die 210 and tape substrate 110a, respectively, for aligning semiconductor die 210 and tape substrate 110a in relation to one another when attaching semiconductor die 210 to tape substrate 110a. Two first alignment keys 240 are disposed at inner portions of semiconductor die 210 corresponding to two corners of semiconductor die 210, respectively, wherein the two corners are separated from one another diagonally. In addition, first alignment keys 240 each have a shape similar to the capital letter “L”. Each of second alignment keys 140 also has a shape similar to the capital letter “L”. In addition, second alignment keys 140 are disposed on substrate portion 110, are disposed outside of corners of semiconductor die 210, and are exposed through opening 150. First and second alignment keys 240 and 140 may have various shapes and may be disposed at various positions of semiconductor die 210 and substrate portion 110, respectively, in accordance with what is suitable for the semiconductor package in which they are disposed.
Tape substrate 110a and semiconductor die 210 are pressed and heated in an aligned state, which is shown in
However, in the embodiment illustrated in
Referring to
In the embodiment illustrated in
Referring to
In the embodiment illustrated in
Referring to
In the embodiment illustrated in
In accordance with the embodiments described above, at least one dummy pattern is formed on a COF type of TAB tape substrate and at least one dummy pattern is formed on a semiconductor die that is to be mounted on a TAB tape substrate to improve the post-attaching alignment of the TAB tape substrate and a semiconductor die. However, embodiments of the invention may also be applied to semiconductor packages in which a semiconductor die is attached to any one of various types of tape substrates.
In a semiconductor package in accordance with an embodiment of the invention, at least one dummy pattern is formed on a semiconductor die and at least one dummy pattern is formed on a tape substrate on which the semiconductor die is mounted so that the post-attaching alignment of the semiconductor die and the tape substrate may be improved, and to reduce deformation of the tape substrate due to pressure and heat. Accordingly, alignment of connection terminals of the semiconductor die and the tape substrate after the semiconductor die and the tape substrate are connected to one another may be improved, and therefore assembly accuracy of the corresponding semiconductor package may be improved.
Although embodiments of the invention have been described herein, various changes may be made to the embodiments by one of ordinary skill in the art without departing from the scope of the invention as defined by the accompanying claims.
Claims
1. A semiconductor package comprising:
- a semiconductor die;
- first connection terminals disposed on a first surface of the semiconductor die;
- a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals;
- a first alignment member disposed on the first surface of the semiconductor die; and,
- a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.
2. The semiconductor package of claim 1, wherein the tape substrate is a chip on film type of tape automated bonding (TAB) tape substrate.
3. The semiconductor package of claim 1, wherein the first alignment member has the same shape as at least one of the first connection terminals and at least a portion of the second alignment member has the same shape as at least one of the second connection terminals.
4. The semiconductor package of claim 1, wherein the first alignment member is disposed at a center portion of the first surface of the semiconductor die or on a portion of the first surface of the semiconductor die where the first connection terminals are disposed.
5. The semiconductor package of claim 1, wherein:
- the first alignment member comprises a dummy bump;
- the second alignment member comprises a pair of dummy leads; and,
- at least a portion of the dummy bump is interposed between the dummy leads.
6. The semiconductor package of claim 1, wherein:
- the first alignment member comprises a pair of dummy bumps;
- the second alignment member comprises a dummy lead; and,
- at least a portion of the dummy lead is interposed between the dummy bumps.
7. The semiconductor package of claim 1, wherein:
- the first alignment member comprises a cylindrical dummy pattern; and,
- the second alignment member comprises an annular dummy pattern surrounding at least a portion of the cylindrical dummy pattern.
8. The semiconductor package of claim 1, wherein:
- the second alignment member comprises a cone-like dummy pattern; and,
- the first alignment member comprises an annular dummy pattern surrounding at least a portion of the second alignment member.
9. The semiconductor package of claim 1, wherein a gap between a side surface of the first alignment member and a side surface of the second alignment member is less than about 2 μm.
10. The semiconductor package of claim 1, wherein a side surface of the first alignment member is in contact with a side surface of the second alignment member.
11. The semiconductor package of claim 1, wherein;
- the first connection terminals comprise a plurality of first bumps disposed along a first edge of the semiconductor die and a plurality of second bumps disposed along a second edge of the semiconductor die; and,
- the second connection terminals comprise a plurality of first inner leads disposed corresponding to the first bumps and a plurality of second inner leads disposed corresponding to the second bumps.
12. The semiconductor package of claim 11, wherein the first alignment member is disposed between two of at least one of the first bumps or the second bumps, and the second alignment member is disposed between inner leads of the first inner leads or the second inner leads.
13. The semiconductor package of claim 12, wherein:
- the first alignment member comprises a dummy bump having the same shape as at least one of the first bumps or second bumps; and,
- the second alignment member comprises a dummy inner lead having the same shape as at least one of one inner leads of the first inner leads or the second inner leads.
14. The semiconductor package of claim 12, wherein:
- the first alignment member comprises a pair of dummy bumps;
- the second alignment member comprises a dummy lead; and,
- at least a portion of the dummy lead is interposed between the dummy bumps.
15. The semiconductor package of claim 12, wherein:
- the first alignment member comprises a cylindrical dummy pattern; and,
- the second alignment member comprises an annular dummy pattern surrounding at least a portion of the first alignment member.
16. The semiconductor package of claim 12, wherein:
- the second alignment member comprises a cone-like dummy pattern; and,
- the first alignment member comprises an annular dummy pattern surrounding at least a portion of the second alignment member.
17. The semiconductor package of claim 12, wherein a side surface of the first alignment member is in contact with a side surface of the second alignment member.
18. The semiconductor package of claim 12, wherein a gap between a side surface of the first alignment member and a side surface of the second alignment member is less than about 2 μm.
19. A semiconductor package comprising:
- a semiconductor die;
- first connection terminals disposed on a first surface of the semiconductor die;
- a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals;
- a first alignment member disposed on the first surface of the semiconductor die; and,
- a second alignment member disposed on the substrate portion of the tape substrate,
- wherein at least a portion of the first alignment member is disposed between portions of the second alignment member.
20. A semiconductor package comprising:
- a semiconductor die;
- first connection terminals disposed on a first surface of the semiconductor die;
- a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals;
- a first alignment member disposed on the first surface of the semiconductor die; and,
- a second alignment member disposed on the substrate portion of the tape substrate,
- wherein at least a portion of the second alignment member is disposed between portions of the first alignment member.
Type: Application
Filed: Jul 12, 2007
Publication Date: Mar 27, 2008
Applicant: SAMSUNG ELECTRONICS CO., LTD. (Gyeonggi-do)
Inventors: Na-rae SHIN (Yongin-si), Dong-han KIM (Osan-si)
Application Number: 11/776,734
International Classification: H01L 23/48 (20060101);