MIM transistor
The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.
1. Field of the Invention
The present invention relates to the field of miniaturized electronic components.
2. Description of the Related Art
In the field of voltage controlled integrated electronic components, currently MOS (Metal-Oxide-Semiconductor) type transistors are most commonly used, in which an isolated gate is positioned above a semiconductor portion in which a conducting or non-conducting channel can be formed depending on the biasing of the gate. A distinction is generally made between MOS transistors formed on a semiconductor wafer and MOS transistors formed on a thin semiconducting layer covered by an insulating layer mounted on a silicon wafer (SOI structure).
All of these MOS transistors present diverse problems when it is attempted to reduce their dimensions in order to achieve sizes in the order of several tens of nanometers. Among these problems, there are in particular the following:
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- particular effects known as short channel effects are produced, these effects resulting in only partial control of the channel inversion caused by the field of the gate; this notably results in dependencies between the threshold voltage of the transistor, the length of the gate and the voltage applied between the source and drain of the transistor;
- it is difficult to obtain a gate oxide sufficiently thin and this leads to the use of gate insulating materials having very high dielectric constants which today cause integration problems;
- the cost of SOI type structures is currently very high;
- there are difficulties, in particular when a CMOS structure is used, in other words an N-channel MOS transistor positioned alongside a P-channel MOS transistor, to achieve good isolation between the transistors. Currently, the most common technique consists in using shallow isolation trenches (STI or Shallow Trench Isolation) or using insulating SOI wells, which lead to insulating surfaces between the transistors which have approximately the same surface area as the transistors, thereby resulting in a large area of lost space on the semiconductor chip;
- in general, there are numerous problems in differentiating between the ON and OFF states.
One embodiment provides a new transistor structure allowing at least some of the problems associated with known MOS structures to be resolved.
According to a first embodiment of the present invention, there is provided a transistor comprising a conducting layer, for example a metal layer, having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.
According to one embodiment of the present invention, electrodes are formed on both sides of the insulated gate.
According to a further embodiment of the present invention, the conducting layer is formed on an insulating layer, the insulating layer being formed on a semiconductor substrate.
According to a further embodiment of the present invention, the semiconductor substrate under the transistor is connected to a determined voltage.
According to a further embodiment of the present invention, the surface in contact with the underside of the transistor is treated to have a nanoroughness.
According to a second embodiment of the present invention, there is provided a complementary structure comprising two transistors as described above, formed adjacent to each other, in which the adjacent semiconductor substrate portions under each transistor are formed of opposite conductivity types, these portions being arranged to be biased so that the junction between them is non-conducting.
The foregoing and other features, aspects and advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which:
Embodiments disclosed herein are based on the phenomenon that, when a charge is positioned (or an electric field is applied) close to a metal lattice or to a conducting material, the surface layer of the metal lattice or conducting layer tends to become depleted. This phenomenon is limited to thicknesses in the order of one or two crystalline atomic layers of metal (0.1 to 0.3 nm).
Preferably, as illustrated in
The source voltage will be referred to as VS, the drain voltage as VD, the gate voltage as VG, and the positive supply voltage as Vdd. With the structure of
In the non-conducting state or OFF state, the corresponding voltages are for example VS=0, VD=Vdd, VG=Vdd, and ROFF is then in the region of 1000 ohms or more.
According to another embodiment, a thin metal layer is deposited on an insulating layer having a certain roughness. There are various knowing methods for obtaining a silicon oxide surface having a roughness in the order of a few angstroms, or nanoroughness. For example the oxide surface could be bombarded with argon ions before the metal layer is deposited. It has been shown by simulations that this roughness of the silicon oxide surface appreciably increases the ratio ION/IOFF between the current in the ON state and current in the OFF state.
Transistors described above can be used to provide complementary type structures.
Each of the transistors M1 and M2 comprises, as described above, a very thin conductive layer 2 deposited on an insulating layer 11. Each of the transistors comprises a gate 5 isolated by an insulating layer 6. The transistor M1 comprises a source contact 20 and a drain contact 21. The drain contact 21 also forms the source contact of transistor M2, transistor M2 also comprising a drain contact 22 on the other side of the gate. In the example embodiment shown, transistor M1 is formed on an N-type doped silicon layer 31 and the transistor M2 is formed on a P-type doped silicon layer 32. These layers are formed using known technology relating to integrated circuit implementation on silicon. A contact 33 is formed on the N type silicon layer 31, over an intermediate more highly doped N-type layer 35. In the same way, a contact 34 is formed on the P-type doped silicon layer 32, over an intermediate more highly doped P-type region 36. The gates of the two transistors are together connected to a voltage Vin, the node 21 providing the output OUT of the inverter.
In the state shown in
It will be apparent to those skilled in the art that the embodiment illustrated in
A fundamental advantage of the MIM transistors described above is that an insulating region is no longer necessary between adjacent transistors, which allows a considerable reduction in the integrated surface area.
A further advantage of the disclosed embodiments is that the short channel effect no longer exists due to the channel being very thin and there being practically total control by the gate of the whole length of the channel.
A further advantage of the disclosed embodiments is that the technology is very simple: numerous implantation levels are not necessary and, if necessary, a structure can be provided on the same semiconductor chip as a standard MOS or bipolar transistor structure.
A further advantage of the disclosed embodiments is that the switch speed of the transistor is very fast, being limited only by the relaxation speed of electrons in the metal.
A further advantage of the disclosed embodiments is that the resistance in the conducting state is very low, in other words the current in the conducting state can be high.
The present invention is susceptible to numerous variations and modifications which will appear to the man skilled in the art. In particular, those skilled in the art will select materials that are appropriate to the particular technologies used. Notably, for forming the very thin metal layer, a material such as W, Ni, Mo, Ta, Ti, Pt, having a thickness of 0.2 to 1 nm could for example be used. Metal alloys could also be used, such as Ni—W, Ni—Fe, for which depletion may be greater. Non-metal conducting materials could also be used, which, while having higher resistance, may provide greater depletion.
One embodiment has been presented in the form of a planar transistor. The present invention applies more generally to all structures and all types of transistors in which a depletion effect can be used.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Claims
1. A transistor comprising:
- a conducting layer having a thickness of between 1 and 5 atoms; and
- an insulated gate being formed on at least a portion of the conducting layer.
2. The transistor of claim 1, wherein the conducting layer is formed of metal.
3. The transistor of claim 1, further comprising:
- a first electrode and a second electrode, and the insulated gate being positioned between the first and second electrodes.
4. The transistor of claim 3, wherein the conducting layer extends between the first electrode and the second electrode.
5. The transistor of claim 1, wherein the conducting layer is on an insulating layer such that the insulating layer is between the conducting layer and a semiconductor substrate.
6. The transistor of claim 5, wherein the semiconductor substrate under the transistor is connected to a determined voltage.
7. The transistor of claim 1, further comprising:
- a surface in contact with the conducting layer having a nanoroughness.
8. The transistor of claim 1, wherein the insulated gate includes a gate and an insulating layer between the gate and the conducting layer.
9. The transistor of claim 1, wherein the transistor is integrated into a semiconductor chip.
10. A transistor comprising:
- a conductive layer having a section with a thickness equal to or less than 5 atoms;
- a gate on the section of the conductive layer having the thickness equal to or less than 5 atoms; and
- an insulating layer between the gate and the conductive layer.
11. The transistor of claim 10, further comprising:
- a first electrode and a second electrode on the conductive layer, the gate and insulating layer positioned between and spaced apart from the first electrode and the second electrode.
12. The transistor of claim 10, wherein the gate and the conductive layer are made of metal.
13. The transistor of claim 10, further comprising:
- a substrate under the conductive layer, the substrate comprising a semiconductor substrate and a substrate insulating layer, and the substrate insulating layer positioned between the conductive layer and the semiconductor substrate.
14. The transistor of claim 10, wherein the conductive layer is on a nano-roughened support surface.
15. The transistor of claim 14, further comprising:
- an insulating layer having the nano-roughened support surface.
16. The transistor of claim 9, wherein the insulating layer has a thickness that is sufficiently small such that at least a portion of the conductive layer is depleted so that the transistor is in a non-conducting state when an electric field is applied via the insulated gate.
17. A structure comprising:
- a first transistor including a first conducting layer having a thickness of between 1 and 5 atoms and a first insulated gate being formed on at least a portion of the first conducting layer; and
- a second transistor including a second conducting layer having a thickness of between 1 and 5 atoms and a second insulated gate being formed on at least a portion of the second conducting layer, the second transistor adjacent to the first transistor;
- wherein first and second semiconductor substrate portions under the first and second transistors, respectively, have opposite conductivity types, the first and second semiconductor substrate portions are adjacent one another and configured to be biased so that a junction between the semiconductor substrate portions is non-conducting.
18. The structure of claim 17, where a first material forming the first semiconductor substrate portion is N-type doped silicon and a second material forming the second semiconductor substrate portion is P-type doped silicon.
19. The structure of claim 17, wherein the first material physically contacts the second material.
20. The structure of claim 17, wherein a continuous conducting layer on an insulator forms the first and second conducting layers.
Type: Application
Filed: Sep 25, 2007
Publication Date: Jun 12, 2008
Applicant: STMicroelectronics Crolles 2 SAS (Crolles)
Inventors: Benoit Froment (Bruxelles), Etienne Robilliart (Lumbin)
Application Number: 11/904,305
International Classification: H01L 29/08 (20060101);