Of Field-effect Transistors With Insulated Gate (epo) Patents (Class 257/E29.04)
  • Patent number: 9825126
    Abstract: A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: November 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideyuki Hatta, Naruhisa Miura
  • Patent number: 9437440
    Abstract: A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Patent number: 8928050
    Abstract: An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Prasad Venkatraman, Zia Hossain, Gordon M. Grivna
  • Patent number: 8916851
    Abstract: A graphene-based device can be characterized as including a first electrode comprising graphene, a second electrode comprising graphene, and a potential barrier. The first electrode is physically separated from the second electrode by the potential barrier. The first electrode, second electrode and potential barrier are configured such that the graphene-based device can exhibit non-linear I-V characteristics under application of a voltage bias between the first electrode and the second electrode.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: December 23, 2014
    Inventors: Kurt Eaton, Kimberly Eaton
  • Patent number: 8907405
    Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Reinaldo A. Vega, Hongwen Yan
  • Patent number: 8901614
    Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: December 2, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Michael Stoisiek, Michael Gross
  • Patent number: 8884346
    Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8878308
    Abstract: The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chih Chen, Tsung-Lin Lee, Feng Yuan
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8803224
    Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 12, 2014
    Assignee: SK hynix Inc.
    Inventor: Kyoung Bong Rouh
  • Patent number: 8790998
    Abstract: Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-ha Hong, Kyoung-won Park, Jai-kwang Shin, Jong-seob Kim, Hyuk-soon Choi
  • Patent number: 8772755
    Abstract: A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8772782
    Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Patent number: 8723178
    Abstract: An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: May 13, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Tiesheng Li
  • Patent number: 8674449
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: March 18, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8659059
    Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 25, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove
  • Publication number: 20140042385
    Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aaron D. Franklin, Shu-jen Han, Joshua T. Smith, Paul M. Solomon
  • Patent number: 8648445
    Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Agere Systems LLC
    Inventors: Muhammed Ayman Shibib, Shuming Xu
  • Patent number: 8643137
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 8525147
    Abstract: A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-myoung Lee, Min-sang Kim, Dong-won Kim
  • Patent number: 8445893
    Abstract: An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: May 21, 2013
    Assignee: Trustees of Columbia University in the City of New York
    Inventors: Inanc Meric, Kenneth Shepard, Noah J. Tremblay, Philip Kim, Colin P. Nuckolls
  • Patent number: 8362530
    Abstract: An active region made of Si or SiGe is formed in a surface part of a substrate. A gate electrode is disposed over the active region. A gate insulating film is disposed between the gate electrode and the substrate. A source and a drain are formed in the surface part of the substrate on sides of the gate electrode. A surface of the active region under the gate electrode includes a slope surface being upward from a border of the active region toward an inner side of the active region. The slope surface has a crystal plane equivalent to (331).
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: January 29, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hidenobu Fukutome
  • Patent number: 8324690
    Abstract: A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jyh-Huei Chen
  • Publication number: 20120280204
    Abstract: A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8304307
    Abstract: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Xianfeng Zhou
  • Patent number: 8294238
    Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Takayuki Toba, Yoshiko Kato, Kenji Gomikawa, Haruhiko Koyama
  • Publication number: 20120261645
    Abstract: Disclosed herein is a graphene device having a structure in which a physical gap is provided so that the off-state current of the graphene device can be significantly reduced without having to form a band gap in graphene, and thus the on/off current ratio of the graphene device can be significantly increased while the high electron mobility of graphene is maintained.
    Type: Application
    Filed: July 5, 2011
    Publication date: October 18, 2012
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Byung Jin CHO, Jeong Hun Mun
  • Patent number: 8288830
    Abstract: A semiconductor device includes: an active region defined by a device isolation layer on and/or over a substrate; a second conductive well on and/or over the active region; an extended drain formed at one side of the second conductive well; a gate electrode on and/or over the second conductive well and the extended drain; and a source and a drain formed at both sides of the gate electrode, in which extended regions are formed at the corners of the second conductive well under the gate electrode.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 16, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jong-Min Kim, Jae-Hyun Yoo, Chan-Ho Park
  • Publication number: 20120217468
    Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 30, 2012
    Applicant: International Business Machines Corporation
    Inventors: Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight, Dureseti Chidambarrao
  • Patent number: 8242556
    Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: August 14, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Koh Yoshikawa, Hiroki Wakimoto, Masahito Otsuki
  • Patent number: 8237233
    Abstract: In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20120168711
    Abstract: A method is provided for forming narrow-waist nanowire (NW) transistors with wide aspect ratio ends. The method provides a semiconductor-on-insulator wafer. The top semiconductor layer is etched to form a first pad, a second pad, and a plurality of narrow-waist semiconductor bridges. Each semiconductor bridge has two ends, each with a first width, attached to the first and second pads, and a mid-section less than the first width. A channel is formed in a center portion of each mid-section, a drain interposed between the channel and the first end, a source interposed between the channel and the second end, and a gate dielectric surrounding the channel and adjacent portions of the source and drain. A gate electrode is formed surrounding the gate dielectric. The semiconductor bridge ends are etched from the first and second pads, forming a plurality of narrow-waist semiconductor NW transistors.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Inventors: Mark Albert Crowder, Paul J. Schuele
  • Patent number: 8212329
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Grant
    Filed: November 6, 2010
    Date of Patent: July 3, 2012
    Assignee: Alpha and Omega Semiconductor Inc.
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 8187943
    Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: May 29, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandra Cascio, Giuseppe Curro
  • Publication number: 20120097960
    Abstract: A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Patent number: 8133789
    Abstract: A silicon carbide power MOSFET having a drain region of a first conductivity type, a base region of a second conductivity type above the drain region, and a source region of the first conductivity type adjacent an upper surface of the base region, the base region including a channel extending from the source region through the base region adjacent a gate interface surface thereof, the channel having a length less than approximately 0.6 ?m, and the base region having a doping concentration of the second conductivity type sufficiently high that the potential barrier at the source end of the channel is not lowered by the voltage applied to the drain. The MOSFET includes self-aligned base and source regions as well as self-aligned ohmic contacts to the base and source regions.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: March 13, 2012
    Assignee: Purdue Research Foundation
    Inventors: James A. Cooper, Maherin Matin
  • Publication number: 20120049160
    Abstract: The disclosed field-effect transistor has a graphene channel, and does not exhibit ambipolar properties. Specifically, the field-effect transistor has a semi-conducting substrate; a channel including a graphene layer disposed on the aforementioned semiconductor substrate; a source electrode and drain electrode comprising a metal; and a gate electrode. The aforementioned channel and the aforementioned source and drain electrodes comprising a metal are connected via a semiconductor layer.
    Type: Application
    Filed: April 1, 2010
    Publication date: March 1, 2012
    Inventors: Eiichi Sano, Taiichi Otsuji
  • Patent number: 8120073
    Abstract: A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Titash Rakshit, Stephen M. Cea, Jack T Kavalieros, Ravi Pillarisetty
  • Patent number: 8102006
    Abstract: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Xianfeng Zhou
  • Patent number: 8080839
    Abstract: An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Sandip Tiwari, Moon-Kyung Kim, Joshua Mark Rubin, Soo-Doo Chae, Choong-Man Lee, Ravishankar Sundararaman
  • Patent number: 8049279
    Abstract: A semiconductor device includes a substrate of a first conductivity type, a first doped region of a second conductivity type, at least one second doped region of the first conductivity type, a third doped region of the second conductivity type, a gate structure, and at least one contact. The first and the second doped regions are configured in the substrate, and each second doped region is surrounded by the first doped region. The third doped region is configured in the substrate outside of the first doped region. The gate structure is disposed on the substrate between the first and third doped regions. The contact is disposed on the substrate. Each contact connects, in a direction parallel to the gate structure, the first and second doped regions alternately.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: November 1, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Han-Min Huang, Chin-Lung Chen
  • Publication number: 20110260136
    Abstract: A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 27, 2011
    Inventors: Ji-myoung Lee, Min-sang Kim, Dong-won Kim
  • Publication number: 20110233512
    Abstract: Vertical integrated field effect transistor circuits and methods are described which are fabricated from Silicon, Germanium, or a combination Silicon and Germanium based on nanowires grown in place on the substrate. By way of example, vertical integrated transistors are formed from one or more nanowires which have been insulated, had a gate deposited thereon, and to which a drain is coupled to the exposed tips of one or more of the nanowires. The nanowires are preferably grown over a surface or according to a desired pattern in response to dispersing metal nanoclusters over the desired portions of the substrate. In one preferred implementation, SiCl4 is utilized as a gas phase precursor during the nanowire growth process. In place nanowire growth is also taught in conjunction with structures, such as trenches, while bridging forms of nanowires are also described.
    Type: Application
    Filed: January 16, 2008
    Publication date: September 29, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Peidong Yang, Joshua Goldberger, Allon Hochbaum, Rong Fan, Rongrui He
  • Publication number: 20110140085
    Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.
    Type: Application
    Filed: November 18, 2010
    Publication date: June 16, 2011
    Inventors: Andrew P. Homyk, Michael D. Henry, Axel Scherer, Sameer Walavalkar
  • Publication number: 20110089474
    Abstract: An active region made of Si or SiGe is formed in a surface part of a substrate. A gate electrode is disposed over the active region. A gate insulating film is disposed between the gate electrode and the substrate. A source and a drain are formed in the surface part of the substrate on sides of the gate electrode. A surface of the active region under the gate electrode includes a slope surface being upward from a border of the active region toward an inner side of the active region. The slope surface has a crystal plane equivalent to (331).
    Type: Application
    Filed: December 9, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hidenobu Fukutome
  • Patent number: 7923788
    Abstract: A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Ohguro, Takashi Izumida, Satoshi Inaba, Kimitoshi Okano, Nobutoshi Aoki
  • Patent number: 7915685
    Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventor: Guy Moshe Cohen
  • Patent number: 7915682
    Abstract: Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman
  • Patent number: 7910950
    Abstract: In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: March 22, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Patent number: 7902635
    Abstract: Improved radio frequency gain in a silicon-based bipolar transistor may be provided by adoption of a common-base configuration, preferably together with excess doping of the base to provide extremely low base resistances boosting performance over similar common-emitter designs.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: March 8, 2011
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Ningyue Jiang