With Specific Electrical Feedthrough Structure Patents (Class 257/698)
  • Patent number: 11062990
    Abstract: A semiconductor package using an insulating frame of various is disclosed. The insulating frame has a through hole therein, and the semiconductor chip is mounted in the through hole. Further, a via hole is provided in the periphery of the through hole, and a via contact filling the via hole is provided. Whereby the pad of the semiconductor chip is electrically connected to the via contact through the distribution layer. Further, an adhesive buffer layer for increasing the adhesive force is introduced into the upper portion of the insulating frame.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 13, 2021
    Inventors: Yongtae Kwon, Junkyu Lee, Jaecheon Lee, Mina Yoon
  • Patent number: 11037880
    Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myung Sam Kang, Yong Koon Lee, Young Gwan Ko, Young Chan Ko, Moon Il Kim
  • Patent number: 11031352
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Patent number: 11024564
    Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Osvaldo Jorge Lopez
  • Patent number: 11018073
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Patent number: 11004786
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 10991676
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: April 27, 2021
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10978400
    Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: Eric Saugier
  • Patent number: 10973122
    Abstract: A printed circuit board includes a top conducting layer, an escaping layer, one or more first reference layers interposed between the top conducting layer and the escaping layer, and a second reference layer disposed under the escaping layer. The top conducting layer includes two connecting pads for receiving a pair of differential signals. A pair of vias are provided to extend vertically to penetrate the one or more first reference layers, the escaping layer, and the second reference layer. The vias connects the top conducting layer with the escaping layer. Each of the one or more first reference layers includes a continuous via void surrounding the pair of vias. The second reference layer includes two round via voids each surrounding one of the vias. The second reference layer includes a conductive film disposed between the two round via voids.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 6, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Melvin K. Benedict
  • Patent number: 10957652
    Abstract: A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 23, 2021
    Assignee: TAIYO YUDENCO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yoshiki Hamada
  • Patent number: 10950535
    Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: March 16, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Min Wang, Pu-Ju Lin, Cheng-Ta Ko
  • Patent number: 10930525
    Abstract: A carrier substrate includes a core layer and at least one unit pattern portion, and the unit pattern portion includes a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, a second metal layer disposed on the release layer, and a third metal layer disposed on the second metal layer and covering side surfaces of the release layer, and a method of manufacturing a semiconductor package using the carrier substrate.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yieok Kwon, Ikjun Choi
  • Patent number: 10930596
    Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventor: John S. Guzek
  • Patent number: 10913655
    Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 9, 2021
    Assignee: SiTime Corporation
    Inventors: Pavan Gupta, Aaron Partridge, Markus Lutz
  • Patent number: 10903183
    Abstract: A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: January 26, 2021
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 10886316
    Abstract: A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 5, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Norihiro Muramatsu, Katsunori Nozawa
  • Patent number: 10854528
    Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
  • Patent number: 10854650
    Abstract: A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 1, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Norihiro Muramatsu, Katsunori Nozawa
  • Patent number: 10854577
    Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Shien Chen, Shou-Cheng Hu
  • Patent number: 10847746
    Abstract: A display device includes a flexible base layer including a first portion and a second portion disposed around the second portion; a display unit disposed on a first surface of the first portion and including a light emitting element; a driving circuit disposed on a first surface of the second portion and including a driving chip; a support member attached to a second surface of the first portion and a second surface of the second portion; and an adhesive member disposed between the flexible base layer and the support member, wherein the adhesive member includes a first adhesive member having a first elastic modulus and a second adhesive member having a second elastic modulus that is higher than the first elastic modulus, and the second adhesive member overlaps the driving circuit.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee
  • Patent number: 10833028
    Abstract: A thin-film capacitor structure (50) is joined to an electrode pad surface (2S) of an area array integrated circuit (2) having a plurality of electrode pads (3G, 3P, 3S) arranged in an area array on the electrode pad surface (2S). The thin-film capacitor structure (50) includes a thin-film capacitor (10) including a first sheet electrode (11), a second sheet electrode (13), and a thin-film dielectric layer (12) formed between the first sheet electrode (11) and the second sheet electrode (12), a first insulating film (21), a second insulating film (22), and a plurality of through holes (30P, 30G, 30S). The plurality of through holes (30P, 30G, 30S) are bored from the first insulating film (21) to the second insulating film (22) through the thin-film capacitor (10) and formed in positions corresponding to the plurality of electrode pads (3G, 3P, 3S).
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: November 10, 2020
    Assignee: NODA SCREEN CO., LTD.
    Inventor: Seisei Oyamada
  • Patent number: 10825763
    Abstract: A power module of double-faced cooling includes: an upper substrate; a lower substrate on which a plurality of semiconductor chips are disposed; and a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other, and disposed on the lower substrate to be equally distanced from each of the semiconductor chips. Power is supplied to the semiconductor chips on the lower substrate through the upper substrate and the first spacer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: November 3, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Young Seok Kim, Kyoung Kook Hong
  • Patent number: 10818566
    Abstract: A circuit module (101) includes a substrate (1) having a principal surface (1a), a first component (6) mounted on the principal surface (1a), and a sealing resin portion (3) that covers at least a side surface of the first component (6) while covering the principal surface (1a). The first component (6) includes an empty portion (6c) and a connection portion (6b) exposed to the empty portion (6c). The sealing resin portion (3) is arranged to avoid at least a part of a region that is included in an upper surface of the first component (6) and corresponds to the empty portion (6c).
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 27, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ken Okada, Kazushige Sato, Shingo Funakawa, Katsuhiko Fujikawa, Nobumitsu Amachi
  • Patent number: 10818571
    Abstract: The present application discloses a packaging structure for a power module, comprising: a heat dissipation substrate; at least one first power device disposed on a first substrate having an insulating layer, the first substrate disposed on the heat dissipating substrate; and at least one second power device including a jumping electrode having a jumping potential, wherein the at least one second power device is disposed on at least one second substrate having an insulating layer, and the at least one second substrate is disposed on the first substrate, to reduce a parasitic capacitance between the jumping electrode and the heat dissipation substrate. The packaging structure for the power module according to the present application can reduce the parasitic capacitance between the jumping electrode of the power module and the heat dissipation substrate, thereby greatly reducing the EMI noise of the power module in operation.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: October 27, 2020
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Chao Yan, Yiwen Lu, Jun Liu
  • Patent number: 10818628
    Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 27, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Patent number: 10804174
    Abstract: A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a continuous loop around upper edges of the walls; a sensitive component that is bonded within the cavity; and a non-magnetic lid that is sealed to the seal ring to close the cavity by a metallic seal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 13, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Marco Francesco Aimi
  • Patent number: 10796984
    Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 6, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Raymond Albert Narvadez, Ernesto Antilano, Jr.
  • Patent number: 10770364
    Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 8, 2020
    Assignee: XILINX, INC.
    Inventors: Hong Shi, Suresh Ramalingam, Siow Chek Tan, Gamal Refai-Ahmed
  • Patent number: 10763016
    Abstract: A method for manufacturing a chip component includes forming an element, which includes a plurality of element parts, on a substrate. A plurality of fuses are formed, for disconnectably connecting each of the plurality of element parts to an external connection electrode. The external connection electrode, which is arranged to provide external connection for the element, is formed by electroless plating on the substrate.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: September 1, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hiroshi Tamagawa, Hiroki Yamamoto, Katsuya Matsuura, Yasuhiro Kondo
  • Patent number: 10733930
    Abstract: A multi-layer device including device layers connected by an interposer. For example, an electronic display may include a light emitting diode (LED) layer including LEDs and a control circuitry layer to provide control signals to the LEDs. The electronic display further includes an interposer positioned between the LED layer and the control circuitry layer. The interposer includes a substrate and an array of conductive pillars extending through the substrate. The conductive pillars electrically connect the LED layer with the control circuitry layer. Bonding layers may be formed on the interposer and a corresponding side of a device layer to facilitate a hybrid bonding process that electrically connects contacts of the device layer to the conductive pillars and joins the bonding layers to attach the device layer to the interposer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 4, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: John Michael Goward
  • Patent number: 10726996
    Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and internal electrodes with external electrodes disposed on one surface of the body, wherein the external electrodes include a first electrode layer disposed on one surface of the body, in contact with the internal electrodes, and including titanium nitride (TiN), and a second electrode layer disposed on the first electrode layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Hun Han, Dong Joon Oh, Sung Min Cho, Chang Hak Choi, Seung Mo Lim, Woong Do Jung
  • Patent number: 10720338
    Abstract: A low temperature cofired ceramic substrate comprises a plurality of dielectric layers, at least one inner conductor layer, a plurality of bond pads, and a solder mask. The dielectric layers are formed from ceramic material and placed one on top of another to form a stack. The inner conductor is formed from electrically conductive paste and positioned on an upper surface of at least one inner dielectric layer. The bond pads are positioned on an outer surface of the stack. Each bond pad is formed from a plurality of conductive sublayers of thin film metal stacked one on top of another, with each conductive sublayer being formed from a different metal. The solder mask is positioned on the same outer surface of the stack as the bond pads and includes a plurality of openings, with each opening exposing at least a portion of one of the bond pads.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 21, 2020
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Barbara Young, Randy Hamm
  • Patent number: 10680518
    Abstract: A power converter module includes an active metal braze (AMB) substrate, power converter circuitry, and a housing. The AMB substrate includes an aluminum nitride base layer, a first conductive layer on a first surface of the aluminum nitride base layer, and a second conductive layer on a second surface of the aluminum nitride base layer opposite the first surface. The power converter circuitry includes a number of silicon carbide switching components coupled to one another via the first conductive layer. The housing is over the power converter circuitry and the AMB substrate. By using an AMB substrate with an aluminum nitride base layer, the thermal dissipation characteristics of the power converter module may be substantially improved while maintaining the structural integrity of the power converter module.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 9, 2020
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Adam Barkley, Henry Lin, Marcelo Schupbach
  • Patent number: 10679955
    Abstract: A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 9, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Thomas A. Kim, Kyu Bum Han
  • Patent number: 10672748
    Abstract: A composite structure is a stack of thinned substrates each having a plurality of active devices of the same or different technologies. An assembled carrier substrate includes die assembled into cavities formed on the carrier substrate such that when the die rest within the cavity, a gap is formed between a bottom surface of the die and a bottom surface of the cavity. This gap removes contact stress applied to the bottom of the die. Another gap can also be formed above the die. Either gap can be filled with a low-stress material. A yield improvement process functionally and physically partitions a conceptual large area die into an array of separate die modules of smaller area. The separate die modules are assembled into an array of cavities formed in a carrier substrate and interconnected to achieve a combined functionality equivalent to the functionality of the conceptual large area die.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: June 2, 2020
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventor: Pirooz Parvarandeh
  • Patent number: 10564374
    Abstract: An electro-optical interconnection platform is provided. The platform includes an interface medium; a plurality of optical pads; a plurality of electrical pads; and at least one beam coupler adapted to optically couple at least one pair of optical pads of the plurality of optical pads, wherein the at least one pair of optical pads are placed on opposite sides of the interface medium.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: February 18, 2020
    Assignee: Teramount Ltd.
    Inventors: Abraham Israel, Hesham Taha
  • Patent number: 10553458
    Abstract: The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: February 4, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yuedong Qiu, Chengchung Lin
  • Patent number: 10546927
    Abstract: Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 28, 2020
    Assignee: INTEL Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung
  • Patent number: 10524349
    Abstract: A printed circuit board with built-in vertical heat dissipation ceramic block, and an electrical assembly are disclosed. The electrical assembly includes the board and a plurality of electronic components. The printed circuit boards includes a dielectric material layer defining at least one through hole, at least one ceramic block corresponding to the through hole, at least one fixing portion for joining the ceramic block to the through hole of the dielectric material layer, a metal circuit layer provided on upper surfaces of the dielectric material layer and the ceramic block, and a high thermal conductivity layer provided on lower surfaces of the dielectric material layer and the ceramic block. The printed circuit board allows the location and size of the ceramic block to be modified according to requirements, so as to implement complicated circuit designs, achieve good effect of thermal conduction, control thermal conduction path, and reduce manufacturing cost.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 31, 2019
    Assignees: ICP Technology Co., Ltd., Xiamen Sentecee E&E Co., Ltd.
    Inventors: Ho-Chieh Yu, Cheng-Lung Liao, Chun-Yu Lin, Jason An-Cheng Huang
  • Patent number: 10522449
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10516092
    Abstract: A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jon Gregory Aday, Hong Bok We, Steve Joseph Bezuk, Nicholas Ian Buchan
  • Patent number: 10515929
    Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
  • Patent number: 10515918
    Abstract: A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Teck Kheng Lee
  • Patent number: 10510673
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Yi-Wen Wu
  • Patent number: 10490449
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Il-Seok Son, Colin T. Carver, Paul B. Fischer, Patrick Morrow, Kimin Jun
  • Patent number: 10475752
    Abstract: A semiconductor package structure includes a substrate, a chip, bumps, an encapsulation layer and a thermal expansion-matching layer. The chip is located on a top surface of the substrate. The bumps electrically connect the chip and the inner connection pads of the substrate. The encapsulation layer covers the bumps, the chip and the top surface of the substrate. The thermal expansion-matching layer covers the whole top surface of the encapsulation layer, and exposes the side surfaces of the encapsulation layer. The thermal expansion coefficient of the thermal expansion-matching layer is different from that of the encapsulation layer. The side surface of the thermal expansion-matching layer is flush with that of the encapsulation layer. The thermal expansion-matching layer balances the inner stresses caused by the difference of the thermal expansion. Thus, the invention reduces the warpage problem of the formed package.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 12, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Che-Wei Hsu
  • Patent number: 10475746
    Abstract: One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 12, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Akihiko Hatasawa
  • Patent number: 10461022
    Abstract: A semiconductor structure includes a first die including a first surface and a second surface opposite to the first surface; a molding surrounding the first die; a first via extended through the molding; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer; and a second die disposed over the molding, wherein the second die is electrically connected to the first via.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien Hsun Lee
  • Patent number: 10446541
    Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Klaus Reingruber
  • Patent number: 10438896
    Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 8, 2019
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Zun Zhai