With Specific Electrical Feedthrough Structure Patents (Class 257/698)
  • Patent number: 10325891
    Abstract: The fan-out semiconductor package includes: a metal member including a metal plate having a first through-hole and second through-holes and metal posts disposed in the second through-holes; a semiconductor chip disposed in the first through-hole; an encapsulant covering at least portion of each of the metal member and the semiconductor chip and filling at least portions of each of the first and second through-holes; a wiring layer disposed on the encapsulant; first vias electrically connecting the wiring layer and the connection pads to each other; and second vias electrically connecting the wiring layer and the metal posts to each other, wherein a height of the second vias is greater than that of the first vias or a thickness of the metal plate is the same as that of the metal post.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 18, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hyun Lim, Han Kim, Eun Jung Jo, Jung Ho Shim, Sang Jong Lee, Hyung Joon Kim
  • Patent number: 10327335
    Abstract: A connection structure includes: a wiring board including a plurality of first electrodes that are arranged on a principal surface; a molded interconnect device (MID) made of a non-electroconductive resin as a base material, the MID including a side surface and a bottom surface, the bottom surface being parallel to the principal surface of the wiring board and including a plurality of arranged second electrodes, and the side surface being perpendicular to the principal surface of the wiring board; and a plurality of electroconductive members each made of an electroconductive paste, each of the electroconductive members electrically connecting each of the plurality of first electrodes to each of the plurality of second electrodes, in which the plurality of electroconductive members are housed in respective reservoir sections formed by the second member and are not in contact with the non-electroconductive resin.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 18, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Takahiro Shimohata
  • Patent number: 10319659
    Abstract: Implementations of semiconductor packages may include: a substrate comprising a first side and a second side and a hole in the substrate. The hole extending from the first side to the second side of the substrate and positioned in a center of the substrate. The semiconductor packages may also include a bushing around the hole to the first side of the substrate. The semiconductor packages may also include a plurality of pin holders arranged and coupled on the substrate. The semiconductor package may also include a molding compound at least partially encapsulating the substrate, encapsulating a side surface of the bushing, and encapsulating a plurality of side surfaces of the plurality of pin holders.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, C H Chew, Yushuang Yao
  • Patent number: 10319667
    Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
  • Patent number: 10297542
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 10297570
    Abstract: An adhesive with self-connecting interconnects is provided. The adhesive layer provides automatic 3D joining of microelectronic components with a conductively self-adjusting anisotropic matrix. In an implementation, the adhesive matrix automatically makes electrical connections between two surfaces that have opposing electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventor: Belgacem Haba
  • Patent number: 10290590
    Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Tzu-Jui Fang, Hsi-Kuei Cheng, Chih-Kang Han, Yi-Jen Lai, Hsien-Wen Liu, Yi-Jou Lin
  • Patent number: 10236275
    Abstract: A die stack having a second die is stacked vertically on top of a first die. A first plurality of test pads is located along a first edge of the first die. A second plurality of test pads is located along a second edge of the first die. The first edge of the first die is parallel to the second edge of the first die. A third plurality of test pads is located along a first edge of the second die. A fourth plurality of test pads is located along a second edge of the second die. The first edge of the second die is parallel to the second edge of the second die. The first edge of the first die and the second edge of the first die are perpendicular to the first edge of the second die and the second edge of the second die.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: March 19, 2019
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 10230183
    Abstract: The invention relates to an electric interface, in particular an interposer, having a first connection plane with at least one first contact surface pair, each of which has a first and second contact surface, and a second connection plane with at least one second contact surface pair, each of which has a third and a fourth contact surface. For each of a first and second contact surface pair, a first electric connection electrically connects the first contact surface of the first connection plane to the third contact surface of the second connection plane, and a second electric connection electrically connects the second contact surface of the first connection plane to the fourth contact surface of the second connection plane.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 12, 2019
    Assignee: Rosenberger Hochfrequenztechnik GmbH & Co. KG
    Inventor: Sandeep Sankararaman
  • Patent number: 10224302
    Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventor: Xinhua Wang
  • Patent number: 10217950
    Abstract: A stretchable film includes a first region including a plurality of first patterns having a concave polygonal shape. The stretchable film also includes a second region including a plurality of second patterns having a concave polygonal shape. The stretchable film further includes a buffer region between the first region and the second region.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 26, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye-Jin Joo, Won-Il Choi, Jong-Ho Hong
  • Patent number: 10206286
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10192802
    Abstract: Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Scott Jewler
  • Patent number: 10185862
    Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a substrate comprising a dielectric layer and a wiring pattern embedded in and exposed from the dielectric layer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 22, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Seung Mo Kim, Chang Hun Kim, Jung Hwa Kim, Se Man Oh
  • Patent number: 10181454
    Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: January 15, 2019
    Assignee: ATI Technologies ULC
    Inventor: Changyok Park
  • Patent number: 10177086
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: January 8, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
  • Patent number: 10157859
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shou-Zen Chang, Chi-Ming Huang, Kai-Chiang Wu, Sen-Kuei Hsu, Hsin-Yu Pan, Han-Ping Pu, Albert Wan
  • Patent number: 10157868
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Jung Byun, Byung Ho Kim, Pyung Hwa Han, Joo Young Choi, Ung Hui Shin
  • Patent number: 10157884
    Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Shien Chen, Yen-Chang Hu
  • Patent number: 10141244
    Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: November 27, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Wuzhi Zhang, Xiaojun Chen, Xuanjie Liu, Haifang Zhang
  • Patent number: 10141257
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 10141275
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 27, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po Chun Lin
  • Patent number: 10128193
    Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Ching-Yao Lin, Ming-Da Cheng, Ching-Hua Hsieh
  • Patent number: 10115693
    Abstract: One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 30, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Akihiko Hatasawa
  • Patent number: 10115646
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 30, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Juergen Hoegerl, Edward Fuergut
  • Patent number: 10109584
    Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Uei-Ming Jow, Young Kyu Song, Jung Ho Yoon, Jong-Hoon Lee, Xiaonan Zhang
  • Patent number: 10103134
    Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 16, 2018
    Inventors: Wei Zhou, Aibin Yu, Zhaohui Ma, Sony Varghese, Jonathan S. Hacker, Bret K. Street, Shijian Luo
  • Patent number: 10090780
    Abstract: A capacitive transducer includes a substrate having a first surface and a second surface opposite the first surface, the substrate including a through wire extending therethrough between the first surface and the second surface, and a cell on the first surface, the cell including a first electrode and a second electrode spaced apart from the first electrode with a gap between the first electrode and the second electrode. Conductive protective films are disposed over surfaces of the through wire on the first surface side and the second surface side of the substrate.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: October 2, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinan Wang, Yutaka Setomoto
  • Patent number: 10079212
    Abstract: In order to restrict cracking or the like in a connection member such as solder, provided is a semiconductor device including a first component; a second component that is arranged on a front surface of the first component; and a connection portion that is provided between the first component and the second component and connects the second component to the first component. A first groove and a second groove having different shapes are formed in the front surface of the first component at positions opposite a first corner and a second corner of the second component, and the connection portion is also formed within the first groove and the second groove.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Takizawa
  • Patent number: 10068887
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 10068847
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 4, 2018
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 10049928
    Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 10037966
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iwasaki, Takeumi Kato, Takanori Okita, Yoshikazu Shimote, Shinji Baba, Kazuyuki Nakagawa, Michitaka Kimura
  • Patent number: 10032732
    Abstract: In a switching module structure that includes a low-impedance path to ground, such as a parasitic capacitance of an insulating substrate, a further insulating substrate presenting a parasitic capacitance placed in series with the low impedance current path and a connection of a conductive layer to input voltage rails using a single decoupling capacitor or, preferably, a midpoint of the voltage rails formed by a series connection of decoupling capacitors maintains a large portion of common mode (CM) currents which are due to high dV/dt slew rates of SiC and GaN transistors within the switching module.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 24, 2018
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Christina DiMarino, Dushan Boroyevich, Rolando Burgos, Mark Johnson
  • Patent number: 10032704
    Abstract: A package includes a device die, a molding material molding the device die therein, and a surface dielectric layer at a surface of the package. A corner opening is in the surface dielectric layer. The corner opening is adjacent to a corner of the package. An inner opening is in the surface dielectric layer. The inner opening is farther away from the corner of the package than the corner opening. The corner opening has a first lateral dimension greater than a second lateral dimension of the inner opening.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10026692
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure. The stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked interlacedly. The etching stop layer is formed on a sidewall of the stack structure. An energy gap of the etching stop layer is larger than 6 eV. The conductive structure is electrically connected to at least one of the conductive layers.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: July 17, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10008392
    Abstract: A power semiconductor module is produced by: providing an electrically conductive terminal block having a screw thread, a connecting conductor having first and second sections, a module housing, a circuit carrier having a dielectric insulation carrier and an upper metallization layer on an upper side of the insulation carrier, and a semiconductor component; fitting the semiconductor component on the circuit carrier; producing a firm and electrically conductive connection between the terminal block and the connecting conductor at the first section; producing a material-fit and electrically conductive connection between the circuit carrier or the semiconductor component and the connecting conductor at the second section; and arranging the terminal block and the circuit carrier fitted with the semiconductor component on the module housing so the semiconductor component is arranged in the module housing and the screw thread is accessible from an outer side of the module housing.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: June 26, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alexander Hoehn, Georg Borghoff
  • Patent number: 9985001
    Abstract: A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kim Hong Chen, Szu-Po Huang, Shin-Puu Jeng, Wensen Hung
  • Patent number: 9985411
    Abstract: A light-emitting device includes a base body; light-emitting elements mounted on an upper surface of the base body; a frame body bonded to the upper surface of the base body, the frame body including inner lateral surfaces, outer lateral surfaces, and first through-holes that extend through the frame body in a lateral direction; lead terminals that extend through the first through-holes, and each of which is electrically connected to the light-emitting elements; a cover bonded to the frame body; plate bodies bonded to an outer lateral surface or inner lateral surface of the frame body, each of the plate bodies having one or more second through-holes, wherein each of the lead terminals extends through a respective through-hole; and fixing members, each of which is disposed in a second through-hole and fixes a respective one of the one or more lead terminals.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 29, 2018
    Assignees: NICHIA CORPORATION, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shigeru Matsushita, Katsuya Nakazawa, Eiichiro Okahisa, Kazuma Kozuru
  • Patent number: 9984987
    Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 29, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po Chun Lin
  • Patent number: 9972581
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Patent number: 9941248
    Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chung Yang, An-Jhih Su, Hsien-Wei Chen, Jo-Mei Wang, Wei-Yu Chen
  • Patent number: 9917042
    Abstract: A dielectric element has a plurality of contacts at a first surface and a plurality of first traces coupled thereto which extend in directions parallel to the first surface. A circuit structure made of a plurality of dielectric layers and electrically conductive features thereon includes a plurality of bumps at a first surface which face the contacts of the dielectric element and are joined thereto. Circuit structure contacts at a second surface opposite the first surface are electrically coupled with the bumps through second traces on the circuit structure, the circuit structure contacts configured for connection with a plurality of element contacts of each of a plurality of microelectronic elements, wherein the microelectronic elements can be assembled therewith such that element contacts thereof face and are joined with the circuit structure contacts.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: March 13, 2018
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Sean Moran
  • Patent number: 9911629
    Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 9893218
    Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: February 13, 2018
    Assignee: Optiz, Inc.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 9887167
    Abstract: A package structure includes a carrier defining a cavity in which a die is disposed. A dielectric material fills the cavity around the die. A first conductive layer is disposed over a first surface of the carrier. A first dielectric layer is disposed over an active surface of the die, the first conductive layer and the first surface of the carrier. A first conductive pattern is disposed over the first dielectric layer, and is electrically connected to the first conductive layer and to the active surface of the die. A second dielectric layer is disposed over the second surface of the carrier and defines a hole having a wall aligned with a sidewall of the cavity. A second conductive layer is disposed over the second dielectric layer. A third conductive layer is disposed on the sidewall of the cavity and the wall of the second dielectric layer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 6, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Cheng Lee, Hsing Kuo Tien, Li Chuan Tsai
  • Patent number: 9887145
    Abstract: A meal top stacking package structure and a method for manufacturing the same are provided, wherein the metal top stacking package structure includes a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: February 6, 2018
    Assignee: DAWNING LEADING TECHNOLOGY INC.
    Inventor: Diann-Fang Lin
  • Patent number: 9852928
    Abstract: A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead. A method of manufacturing the semiconductor package and a semiconductor module with integrated ferrite material are also provided.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies AG
    Inventors: Charles Low Khai Yen, Daryl Quake Chin Wern
  • Patent number: 9847170
    Abstract: A multilayer ceramic capacitor may includes a ceramic body in which first and second dielectric layers are layered in a width direction, first and third internal electrodes disposed on the first dielectric layer and partially exposed to an upper surface of the ceramic body, second and fourth internal electrodes disposed on the second dielectric layer and partially exposed to a lower surface of the ceramic body, first and third external electrodes disposed on the upper surface of the ceramic body and connected to the first and third internal electrodes, respectively, second and fourth external electrodes disposed on the lower surface of the ceramic body and connected to the second and fourth internal electrodes, respectively, and a resistance layer disposed on the upper surface of the ceramic body to cover the first and third external electrodes.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Soo Park, Min Cheol Park
  • Patent number: 9837979
    Abstract: An electronic device includes a first conductive pattern and a second conductive pattern that are disposed on a main surface of an insulating substrate, a first electrode pattern that is electrically connected to the first conductive pattern, and a vibrator element that is disposed on the main surface, and the area of a first section in which the first conductive pattern overlaps the first electrode pattern is greater than the area in which the other conductive pattern overlaps the first electrode pattern in a plan view.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 5, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Masayuki Ishikawa, Seiichi Chiba