With Specific Electrical Feedthrough Structure Patents (Class 257/698)
  • Patent number: 11410934
    Abstract: A substrate, a semiconductor package device and a method of manufacturing a semiconductor device package are provided. The substrate includes a low density wiring structure, a first middle density wiring structure and high density wiring structure. The first middle density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure and the first middle density wiring structure are disposed side by side. A line space of a circuit layer of the low density wiring structure is greater than a line space of a circuit layer of the first middle density wiring structure. The line space of the circuit layer of the first middle density wiring structure is greater than a line space of a circuit layer of the high density wiring structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ian Hu, Shin-Luh Tarng
  • Patent number: 11399238
    Abstract: Microphone devices and methods for manufacturing microphone devices that include a substrate having a first surface and a second surface, a cover secured to the first surface of the substrate to form an enclosed back volume, an application specific integrated circuit (ASIC) embedded between the first surface and the second surface of the substrate, a microelectromechanical systems (MEMS) transducer mounted on the first surface of the substrate, and an inductor mounted on the first surface of the substrate.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: July 26, 2022
    Assignee: Knowles Electronics, LLC
    Inventors: Joshua Watson, Karan Jumani, Donald Yochem
  • Patent number: 11398420
    Abstract: A semiconductor package includes a core member having a first surface and a second surface opposing each other, and an external side surface between the first and second surfaces, the core member having a through-hole connecting the first and second surfaces, having a protruding portion that protrudes from the external side surface, and having a surface roughness (Ra) of 0.5 ?m or more, a redistribution substrate on the first surface of the core member, and including a redistribution layer; a semiconductor chip in the through-hole on the redistribution substrate, and having a contact pad electrically connected to the redistribution layer, and an encapsulant on the redistribution substrate, and covering the semiconductor chip and the core member, the protruding portion of the core member having a surface exposed to a side surface of the encapsulant.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungdon Mun, Myungsam Kang, Youngchan Ko, Yieok Kwon, Jeongseok Kim, Gongje Lee, Bongju Cho
  • Patent number: 11393805
    Abstract: One of semiconductor packages includes a substrate and a package structure. The package structure is bonded to the substrate and includes a first redistribution layer structure, a first logic die, a plurality of second logic dies, a first memory die, a first heat conduction block and a first encapsulant. The first logic die and the second logic dies are disposed over and electrically connected to the first redistribution layer structure. The first memory die is disposed over the first logic die and the second logic dies and electrically connected to first redistribution layer structure. The first heat conduction block is disposed over the first logic die and the second logic dies. The first encapsulant encapsulates the first memory die and the first heat conduction block.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee, Liang-Ju Yen
  • Patent number: 11387176
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 12, 2022
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Yuan-Chin Liu
  • Patent number: 11387171
    Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Shou-Cheng Hu, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu, Chen-Shien Chen
  • Patent number: 11367664
    Abstract: In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 21, 2022
    Assignee: Amkor Technology Japan, Inc.
    Inventors: Shojiro Hanada, Shingo Nakamura
  • Patent number: 11362010
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die over a first surface of a redistribution structure. The method also includes forming a first protective layer to surround a portion of the semiconductor die. The method further includes disposing a device element over a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method includes forming a second protective layer to surround a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Liang Lin, Po-Hao Tsai, Po-Yao Chuang, Yi-Wen Wu, Techi Wong, Shin-Puu Jeng
  • Patent number: 11348900
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 31, 2022
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 11335598
    Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Sudipto Naskar, Manish Chandhok, Miriam Reshotko, Rami Hourani
  • Patent number: 11333683
    Abstract: A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a transposed via arrangement within a circuit board for a probe card, where adjacent vias are offset towards each other such that the inductance between the adjacent vias may be reduced to provide a desirable impedance during high frequency signal and/or power transmission.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 17, 2022
    Assignee: Teradyne, Inc.
    Inventor: Brian Brecht
  • Patent number: 11335646
    Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: May 17, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Yu-Ju Liao
  • Patent number: 11322825
    Abstract: An antenna-deco film stack structure includes a deco film including a light-shielding portion and a transmissive portion, a dielectric layer facing the deco film, an antenna pattern disposed on an upper surface of the dielectric layer and disposed under the deco film, the antenna pattern being at least partially covered by the light-shielding portion, and a ground pattern on a lower surface of the dielectric layer to at least partially cover the antenna pattern. The deco film and the antenna pattern are combined to improve radiation reliability and optical property of the antenna pattern. A display device including the antenna-deco film stack structure is also provided.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 3, 2022
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Yun Seok Oh, Han Sub Ryu, Yoon Ho Huh
  • Patent number: 11315843
    Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr
  • Patent number: 11315886
    Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eunkyoung Choi, Suchang Lee, Yunseok Choi
  • Patent number: 11296004
    Abstract: A semiconductor package is provided including a first semiconductor package including a first semiconductor chip. The first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor package is disposed on the first semiconductor package. The second semiconductor package includes a second redistribution layer including a redistribution line. A second semiconductor chip is disposed on the second redistribution layer. A thermal pillar is disposed on the second redistribution layer. A heat radiator is disposed on the second semiconductor package and connected to the thermal pillar. The redistribution line is connected to the first semiconductor chip.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Taewon Yoo, Hyunsoo Chung, Myungkee Chung
  • Patent number: 11282759
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The interposer substrate is disposed over the package substrate. The first semiconductor device and the second semiconductor device are disposed over the interposer substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed over the interposer substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng, Shuo-Mao Chen
  • Patent number: 11282839
    Abstract: A semiconductor device includes an arrive pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connoted to the first source/drain pattern.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmin Kim, Daewon Ha
  • Patent number: 11239208
    Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
  • Patent number: 11240908
    Abstract: Disclosed herein is a thin film capacitor that includes a capacitive insulating film, a first metal film formed on one surface of the capacitive insulating film, and a second metal film formed on other surface of the capacitive insulating film and made of a metal material different from that of the first metal film. The thin film capacitor has an opening penetrating the capacitive insulating film, first metal film, and second metal film. The second metal film is thicker than the first metal film. A first size of a part of the opening that penetrates the first metal film is larger than a second size of a part of the opening that penetrates the second metal film.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 1, 2022
    Assignee: TDK CORPORATION
    Inventors: Kazuhiro Yoshikawa, Yuuki Aburakawa, Tatsuo Namikawa, Kenichi Yoshida, Hitoshi Saita
  • Patent number: 11233001
    Abstract: An interconnect board includes: a first substrate; a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate. The fillet has a raised portion raised from a level of a top surface of the second substrate to a level higher than the top surface of the second substrate.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 25, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shota Miki, Naoki Kobayashi
  • Patent number: 11222865
    Abstract: The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Patent number: 11217460
    Abstract: A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 4, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Makarand Ramkrishna Kulkarni, Tae Kim
  • Patent number: 11217562
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
  • Patent number: 11195971
    Abstract: A glass wiring substrate includes a glass substrate, a first wiring portion formed on a first surface of the glass substrate, a second wiring portion formed on a second surface opposite to the first surface, a through-hole formed in a region of the glass substrate in which the first wiring portion and the second wiring portion are not formed, the through-hole having a diameter on a second surface side larger than a diameter on a first surface side, and a through-hole portion formed in the through-hole, one end portion of the through-hole portion extending to the first wiring portion, the other end portion of the through-hole portion extending to the second wiring portion, in which a wiring pitch P1 of the first wiring portion in the vicinity of the through-hole portion is narrower than a wiring pitch P2 of the second wiring portion in the vicinity of the through-hole portion.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 7, 2021
    Assignee: SONY CORPORATION
    Inventor: Toshihiko Watanabe
  • Patent number: 11183440
    Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 23, 2021
    Assignee: GaN Systems Inc.
    Inventors: Juncheng Lu, Di Chen, Larry Spaziani, Peter Anthony Di Maso
  • Patent number: 11177307
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Patent number: 11177331
    Abstract: A semiconductor device includes: a semiconductor chip including a substrate having a first surface and a second surface, which are opposite to each other; a through hole penetrating the substrate; a first conductive pad on the first surface of the substrate; a first bump formed over and electrically connected to the first conductive pad; a second conductive pad on the second surface of the substrate; a second bump formed over and electrically connected to the second conductive pad; and a connection electrode buried in the through hole, the connection electrode electrically connecting the first bump and the second bump.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 16, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hae Kwan Seo
  • Patent number: 11162814
    Abstract: A position detecting device includes an IC package, a first terminal line, a ground terminal line, a power supply terminal line, a second terminal line, a bypass terminal line, motor terminal lines, and a connector portion. A bypass terminal line is positioned on an opposite side of the ground terminal line across the first terminal line or the second terminal line and is connected to a bypass portion of the ground terminal line which connects to the ground connection portion. In the connector portion, the motor terminal line, the bypass terminal line, the second terminal line, the power supply terminal line, and the first terminal line are placed in this order.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: November 2, 2021
    Assignee: DENSO CORPORATION
    Inventors: Takeshi Ito, Takamitsu Kubota, Yoshiyuki Kono
  • Patent number: 11166379
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventor: Qinglei Zhang
  • Patent number: 11145617
    Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 12, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Ming Chen
  • Patent number: 11138808
    Abstract: A method of processor-aided design of a workholding frame for a manufacturing process includes using a processor to perform operations including receiving, by a processor, first data representing a first three-dimensional (3D) model of an object to be manufactured. The operations further include obtaining, by the processor, second data describing a second 3D model. The second 3D model represents a bounding box having one or more sides adjoining a surface of the object within the first 3D model. The operations further include automatically generating, by the processor and based on the first data and the bounding box, third data indicating one or more parameters of the workholding frame. The workholding frame and the object are to be formed based on the one or more parameters and as a single workpiece from a blank material during a machining process associated with the object.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 5, 2021
    Assignee: THE BOEING COMPANY
    Inventor: Justin Lee Peters
  • Patent number: 11133245
    Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Tsung Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Cheng Yuan Chen
  • Patent number: 11121068
    Abstract: Embodiments of the present disclosure provide an array substrate, a display device, a method for manufacturing an array substrate, a method for manufacturing a display device, and a spliced display device. The array substrate includes: a base substrate in which a through hole is provided; a filling portion disposed in the through hole, including a recessed structure and made from a flexible material; an electrically conductive pattern disposed on the filling portion and at least partially located in the recessed structure; and a film layer disposed on a side of the electrically conductive pattern facing away from the base substrate.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 14, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Muxin Di, Zhiwei Liang, Yingwei Liu, Ke Wang, Zhanfeng Cao, Renquan Gu, Qi Yao, Jaiil Ryu
  • Patent number: 11107767
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Patent number: 11107638
    Abstract: A dye-sensitized solar cell includes: a transparent electrode; a power generation layer on the first main surface of the transparent electrode, including a semiconductor layer, a photosensitizing dye and an electrolyte layer; a counter electrode on the main surface of the power generation layer, having an electrode extraction region, wherein at least a part of the side surfaces of the counter electrode and at least a part of the side surfaces of the power generation layer are positioned coplanar, the electrode extraction region of the counter electrode overlaps with at least a part of the main surface of the power generation layer in a top view, and the side surfaces of the power generation layer are covered with a sealing layer formed extending from one of the transparent electrode and the counter electrode to the other.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidenori Somei, Takeyuki Fukushima
  • Patent number: 11101541
    Abstract: A semiconductor assembly includes a first wiring structure, a first semiconductor die and a first electronic element. The first wiring structure has a first surface. The first semiconductor die is disposed on the first surface of the first wiring structure. The first electronic element is electrically connected to the first wiring structure. The first electronic element includes a first metal layer, a second metal layer and a dielectric material interposed between the first metal layer and the second metal layer. The first metal layer and the second metal layer are substantially perpendicular to the first surface of the first wiring structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11094604
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • Patent number: 11062990
    Abstract: A semiconductor package using an insulating frame of various is disclosed. The insulating frame has a through hole therein, and the semiconductor chip is mounted in the through hole. Further, a via hole is provided in the periphery of the through hole, and a via contact filling the via hole is provided. Whereby the pad of the semiconductor chip is electrically connected to the via contact through the distribution layer. Further, an adhesive buffer layer for increasing the adhesive force is introduced into the upper portion of the insulating frame.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 13, 2021
    Inventors: Yongtae Kwon, Junkyu Lee, Jaecheon Lee, Mina Yoon
  • Patent number: 11037880
    Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myung Sam Kang, Yong Koon Lee, Young Gwan Ko, Young Chan Ko, Moon Il Kim
  • Patent number: 11031352
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Patent number: 11024564
    Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Osvaldo Jorge Lopez
  • Patent number: 11018073
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • Patent number: 11004786
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 10991676
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: April 27, 2021
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10978400
    Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: Eric Saugier
  • Patent number: 10973122
    Abstract: A printed circuit board includes a top conducting layer, an escaping layer, one or more first reference layers interposed between the top conducting layer and the escaping layer, and a second reference layer disposed under the escaping layer. The top conducting layer includes two connecting pads for receiving a pair of differential signals. A pair of vias are provided to extend vertically to penetrate the one or more first reference layers, the escaping layer, and the second reference layer. The vias connects the top conducting layer with the escaping layer. Each of the one or more first reference layers includes a continuous via void surrounding the pair of vias. The second reference layer includes two round via voids each surrounding one of the vias. The second reference layer includes a conductive film disposed between the two round via voids.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 6, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Melvin K. Benedict
  • Patent number: 10957652
    Abstract: A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 23, 2021
    Assignee: TAIYO YUDENCO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yoshiki Hamada
  • Patent number: 10950535
    Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: March 16, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Min Wang, Pu-Ju Lin, Cheng-Ta Ko
  • Patent number: RE49046
    Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Kai-Chiang Wu, Hsien-Wei Chen, Shih-Wei Liang