SDRAM with Reset Function
A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRSP which indicates a time when a mode register is to be loaded with data. The reset circuit activates the Reset_En signal in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the SDRAM IC are powered down.
Latest Hynix Semiconductor Inc. Patents:
This application is a continuation of U.S. application Ser. No. 11/531,370, filed Sep. 13, 2006, which claims the benefit of U.S. Provisional Application No. 60/717,075, filed Sep. 13, 2005, the disclosures of which are incorporated by reference in their entirety for all purposes.
BACKGROUND OF THE INVENTIONThe present invention relates in general to semiconductor integrated circuits (ICs) and more particularly to a reset function in synchronous dynamic random access memories (SDRAMs).
When using personal computers (PCs) or laptop computers, users typically reset the computer upon encountering such unexpected events as a conflict between programs, a virus attack or infection, or a screen hold. To reset the computer, the user typically powers down the computer and then powers it back up. This process takes a significant amount of time as it usually involves rebooting of the computer. Thus, a technique which enables the user to quickly reset the computer without the need to power down the computer is desirable.
BRIEF SUMMARY OF THE INVENTIONIn accordance with an embodiment of the invention, A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRSP which indicates a time when a mode register is to be loaded with data. The reset circuit activates the Reset_En signal in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the SDRAM IC are powered down.
In one embodiment, a duration of the internal reset interval is dependent on when the CKE signal becomes active to indicate that the SDRAM is ready to receive an external command.
In another embodiment, a duration of the internal reset interval is dependent on when the CKE signal becomes active to indicate SDRAM internal initialization is completed.
In another embodiment, the reset circuit comprises a delay circuit configured so that a duration of the Internal Reset Interval is in part dependent upon the propagation delay through the delay circuit.
In another embodiment, an input of the delay circuit is coupled to the CKE signal.
In another embodiment, the reset circuit further comprises a latch circuit configured to prevent the Reset_En signal from changing states when CKE signal makes transitions during predetermined timing periods.
In another embodiment, the reset circuit further comprises a latch circuit configured to render the Reset_En signal non-responsive to CKE signal transitions during the time the external Reset signal is in inactive state.
In another embodiment, the reset circuit further comprises a pull-up circuit configured to bias the latch circuit in a first state in response the MRSP signal becoming active, the first state of the latch circuit rendering the Reset_En signal non-responsive to CKE signal transitions during the time the external Reset signal is in inactive state.
In another embodiment, the low voltage CMOS input buffer includes a two-input logic gate having one input coupled to a supply voltage and the other input coupled to the external Reset signal.
In another embodiment, the reset circuit includes a first two-input NAND gate providing the Reset_En signal at its output and receiving the RST signal at a first input. A second two-input NAND gate has an output coupled to a second input of the first two-input NAND gate, and has a first input coupled to a clock enable signal CKE through an inverting delay circuit. A two-input NOR gate receives the RST signal at a first input and the CKE signal at a second input. A pull-up transistor and a pull-down transistor are serially coupled between a supply voltage and a ground potential, and the pull-down transistor has a gate terminal coupled to an output of the two-input NOR gate. An inverter has its input coupled to the MRSP signal and its output coupled to a gate terminal of the pull-up transistor. A latch circuit is coupled between a second input of the second two-input NAND gate and a node intermediate serially connected pull-up and pull-down transistors.
A further understanding of the nature and the advantages of the invention disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings.
In accordance with an embodiment of the invention, a semiconductor memory IC, such as a synchronous dynamic random access memory (DRAM) and its varieties (e.g., DDR2 and DDR3), includes a logic block coupled to an external reset pin which enables a user to reset the memory IC without the need to power down the IC.
The biasing circuit includes a pull-down circuit which in turn includes a two-input NOR gate 510 and a pull-down transistor 512. The two-input NOR gate 510 receives RST and CKEint signals at its respective input terminals, and the output terminal of NOR gate 510 is coupled to the gate of pull-down transistor 512. Pull-down transistor 512 is coupled between latch circuit 508 and ground potential. The biasing circuit further includes a pull-up circuit which in turn includes an inverter 514 and a pull-up transistor 516. Inverter 514 receives the MRSP signal at its input, and the output of inverter 514 is coupled to the gate of pull-up transistor 516. Pull-up transistor 516 and pull-down transistor 512 are serially coupled between VDD and ground. The node intermediate transistors 512 and 516 are connected to latch 508. As shown, pull-down transistor 512 is an NMOS transistor and pull-up transistor 516 is a PMOS transistor, but they are not limited as such.
When the external Reset signal is asserted low (i.e., becomes active) at time t1 by for example a user, the internal Reset_En signal is driven high (i.e., becomes active) via NAND gate 502 thus initiating the Internal Reset Interval during which a predetermined number of circuit blocks in the memory are powered down. The Internal Reset Interval ends when both inputs of NAND gate 502 are at a high level. Thus, with the Reset signal raised high at time t2 (i.e., Reset signal becomes inactive), the Internal Reset Interval remains active until a predetermined time delay after CKE goes high (i.e., becomes active) at time t3. That is, with the Reset signal in the inactive state, when CKE signal becomes active at time t3, output 518 of delay circuit 506 goes low after a time period corresponding to the propagation delay through inverter chain 506. Output of NAND gate 504 transitions high in response to the low transition at node 518, thus causing Reset_En signal to transition low terminating the Internal Reset Interval. Delay chain 506, in effect, extends the Internal Reset Interval.
During the B time period when the CKE signal is inactive and the Reset signal is active (i.e., are both low), NOR gate 510 turns on pull-down transistor 512, thus causing latch 508 to either maintain a high at the node marked as CKEN or pull node CKEN high if it was previously in the low state. This ensures that during time period C when both CKE and Reset signals are in inactive state, the Reset_En signal is maintained in the active state. At time t4 when the MRSP pulse is generated to initiate the mode register programming, the high going edge of the MRSP pulse causes pull-up transistor 516 to turn on thus causing the CKEN node to transition low. Latch circuit 508 maintains the CKEN node low until both Reset and CKE signals become low again. During the time CKEN node is low, NAND gate 504 prevents the CKE signal transitions from impacting the state of Reset_En signal. Thus, the MRSP pulse after the external CKE signal becomes active ensures that during the time the external Reset signal is high, transitions in external CKE signal do not impact the state of the internal RESET_EN signal.
Thus, in accordance with an embodiment of the invention, a simple reset circuit implemented in a SDRAM enables the SDRAM to be reset via an external Reset pin without the need to power down the SDRAM. The reset circuit uses only 3 input signals to implement the reset function. This feature advantageously enables resetting a PC or laptop computers when certain malfunctions occur without the need to power down the PC.
While the above provides a detailed description of various embodiments of the invention, many alternatives, modifications, and equivalents are possible. For this and other reasons, therefore, the above description should not be taken as limiting the scope of the invention as defined by the claims.
Claims
1. A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC, the SDRAM IC comprising:
- a low voltage CMOS input buffer configured to generate a buffered reset signal RST from the external Reset signal; and
- a reset circuit configured to generate an internal reset signal Reset_En from (a) the RST signal, (b) a clock enable signal CKE which indicates a time when the SDRAM is ready to receive an external command, and (c) a mode register programming signal MRSP which indicates a time when a mode register is to be loaded with data,
- wherein the reset circuit activates the Reset_En signal in response to the external Reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the SDRAM IC are powered down.
2. The SDRAM IC of claim 1 wherein a duration of the internal reset interval is dependent on when the CKE signal becomes active to indicate that the SDRAM is ready to receive an external command.
3. The SDRAM IC of claim 1 wherein a duration of the internal reset interval is dependent on when the CKE signal becomes active to indicate SDRAM internal initialization is completed.
4. The SDRAM IC of claim 1 wherein the reset circuit comprises a delay circuit configured so that a duration of the internal reset interval is in part dependent upon the propagation delay through the delay circuit.
5. The SDRAM IC of claim 4 wherein an input of the delay circuit is coupled to the CKE signal.
6. The SDRAM IC of claim 4 wherein the delay circuit is an inverting delay circuit.
7. The SDRAM IC of claim 1 wherein the reset circuit further comprises a latch circuit configured to prevent the Reset_En signal from changing states when CKE signal makes transitions during predetermined timing periods.
8. The SDRAM IC of claim 1 wherein the reset circuit further comprises a latch circuit configured to render the Reset_En signal non-responsive to CKE signal transitions during the time the external Reset signal is in inactive state.
9. The SDRAM IC of claim 1 wherein the reset circuit further comprises a pull-up circuit configured to bias the latch circuit in a first state in response the MRSP signal becoming active, the first state of the latch circuit rendering the Reset_En signal non-responsive to CKE signal transitions during the time the external Reset signal is in inactive state.
10. The SDRAM IC of claim 1 wherein the input buffer comprises a two-input logic gate having one input coupled to a supply voltage and the other input coupled to the external Reset signal.
11. The SDRAM IC of claim 1 wherein the reset circuit comprises:
- a first two-input NAND gate providing the Reset_En signal at its output and receiving the RST signal at a first input;
- a second two-input NAND gate having an output coupled to a second input of the first two-input NAND gate, the second two-input NAND gate having a first input coupled to a clock enable signal CKE through an inverting delay circuit;
- a two-input NOR gate receiving the RST signal at a first input and the CKE signal at a second input;
- a pull-up transistor and a pull-down transistor serially coupled between a supply voltage and a ground potential, the pull-down transistor having a gate terminal coupled to an output of the two-input NOR gate;
- an inverter having its input coupled to the MRSP signal and its output coupled to a gate terminal of the pull-up transistor; and
- a latch circuit coupled between a second input of the second two-input NAND gate and a node intermediate serially connected pull-up and pull-down transistors.
12. The SDRAM IC of claim 11 wherein the latch circuit comprises two cross-coupled inverters.
Type: Application
Filed: Mar 21, 2008
Publication Date: Sep 4, 2008
Applicant: Hynix Semiconductor Inc. (Ichon-shi)
Inventor: Ihl-Ho Lee (Ichon-shi)
Application Number: 12/052,944
International Classification: G11C 5/14 (20060101); G11C 8/00 (20060101);