DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE
In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors.
This application claims the benefit of U.S. Provisional Application No. 60/913,542, filed Apr. 24, 2007 and U.S. Provisional Application No. 60/941,667, filed Jun. 3, 2007.
BACKGROUND OF THE INVENTIONThe present invention relates to memories, and more particularly to a dynamic random access memory (DRAM) architecture.
Because a DRAM memory cell includes just a single access transistor and a storage capacitor, DRAM offers dramatic density advantages over static random access memory (SRAM), which typically requires a six transistor (6-T) memory cell. In contrast to SRAM, a DRAM cell will only change the voltage on its corresponding bit line slightly during read operations. Having been coupled to the bit line, the storage capacitor in a DRAM cell must be then be restored after a read operation. Thus, DRAM sense amplifiers require a regenerative latching ability to drive the bit line “full rail” after a read operation. If the sense amplifier determines that the storage capacitor was charged to VDD, the bit line is then driven to VDD to restore the charge on the storage capacitor. On the other hand, if the sense amplifier determines that the storage capacitor was not charged, the bit line is grounded to discharge the storage capacitor. Moreover, the charge on DRAM storage capacitors continually leaks away, requiring constant refreshing. SRAM cells require no such refreshing. In addition, because the 6-T SRAM cell can drive its value onto a bit line during read operations, SRAM is generally substantially faster than DRAM.
As a result of the density vs. speed advantages of SRAM and DRAM, SRAM is faster but more expensive and thus reserved for more time-critical operations such as a microprocessor's cache. To reduce costs, the remaining RAM for a microprocessor is then typically implemented as DRAM. However, because DRAM operation speed is constantly being improved, the use of embedded DRAM in integrated circuits is becoming more popular in high-performance applications that traditionally demanded embedded SRAM. Nevertheless, the choice between DRAM and SRAM is often guided by the density vs. speed tradeoffs discussed above. Accordingly, designers strive to increase DRAM density and speed.
The challenges to increasing DRAM density may be better appreciated through discussion of a conventional DRAM 100 illustrated in
The sense amplifier detects the voltage change by comparing the voltage on bit line Bx to a neighboring bit line such as a bit line B. Before this comparison is made, bit lines Bx and B are pre-charged to a voltage such as VDD/2 by pre-charge circuitry. If the comparison indicates that bit line Bx is higher in voltage than bit line B, downstream decoding logic (not illustrated) will assume that the storage capacitor C0 had previously been charged to a supply voltage such as VDD. If the comparison indicates that bit line B is higher in voltage than bit line Bx, the decoding logic will assume that storage capacitor C0 had previously been discharged. In this fashion, a decision is made as to the binary contents of the memory cell. Having read the contents of the memory cell, the sense amplifier will restore the memory cell using a regenerative latch. An analogous access may be made to a 4memory cell comprised of access transistor M1 and a storage capacitor C1 by raising a word line WL1, and so on.
Each bit line has an inherent capacitance that is typically an order of magnitude greater than the capacitance of the storage capacitors. This difference in capacitance is exacerbated as the number of memory cells accessible by a sense amplifier is increased. For example, should DRAM 100 be implemented with an integer number “N” of word lines, the length of the bit lines will have to double the number of bit lines is increased to 2*N (assuming the same semiconductor process dimensions in both cases). The bit line capacitance will thus double as well, thereby decreasing the voltage change when a memory cell is accessed. As a result, the maximum number of memory cell rows per sense amplifier in a conventional trench-capacitor DRAM is limited to, for example, 512 rows per sense amplifier. This maximum number is considerably lower in embedded DRAMs that need to be compatible with standard semiconductor manufacturing processes such as CMOS. In such embedded DRAMs, the storage cell cannot be formed using a trench capacitor such that the amount of charge that may be stored in the storage cell is reduced. For example, if an embedded DRAM has its storage cells implemented using transistors, the maximum number is typically around 8 to 16 rows. Thus, embedded DRAMs are particularly sensitive to bit-line-capacitance-density-limiting-issues.
Another hindrance to increasing density is the capacitance of the access transistor. For example, as discussed with regard to
Another factor in increasing density is the non-ideal characteristic of sense amplifiers. A conventional sense amplifier 200 is illustrated in
Should both differential inputs, however, be at the same voltage (such as a pre-charge voltage VDD/2), the regenerative latch operation just described may not take place correctly. Instead, because of offset imperfections in the differential amplifier, P0 (for example) output may be driven higher than N0 despite the equal voltages at the inputs. In turn, this offset limits the sensitivity of the sense amplifier operation. For example, suppose bit line B should be higher in voltage than bit line Bx during a read operation. If the storage capacitance is too small with regard to other effects such as bit line capacitance, the offset within the differential amplifier may drive the regenerative latch to pull output N full rail and ground output P, leading to an erroneous reading.
As discussed above, the storage capacitance vs. bit line capacitance is a limiting factor for DRAM density. By increasing the storage capacitance, a sense amplifier can better decide what binary contents are being stored. However, the increased storage capacitance generally leads to increased memory cell size, thereby diminishing density.
SUMMARYThis section summarizes some features of the invention. Other features are described in the subsequent sections.
In accordance with an embodiment of the invention, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors.
In accordance with another embodiment of the invention, a method of operating a DRAM, wherein the DRAM includes a plurality of memory cells, each memory cell including a storage capacitor having a first terminal formed by signal-bearing conductors for the DRAM is provided. The method includes the acts of writing a first binary value into a first one of the storage capacitors by grounding a second opposing terminal of the storage capacitor while charging at least one of the signal-bearing conductors that form the first terminal to a power supply voltage; and writing a second binary value into a second one of the storage capacitors by charging a second opposing terminal of the storage capacitor while grounding at least one of the signal-bearing conductors that form the first terminal.
In accordance with another embodiment of the invention, a DRAM is provided that includes a plurality of memory cells, each memory cell including a storage capacitor having a first terminal coupled to an access transistor and a second terminal coupled to at least one signal-bearing conductor for the DRAM, wherein the DRAM is configured to charge the at least one signal-bearing conductor to a power supply voltage if the DRAM is writing a binary value into the memory cell such that the first terminal is grounded, and wherein the DRAM is further configured to ground the at least one signal-bearing conductor if the DRAM is writing a binary value into the memory cell such that the first terminal is charged to a power supply voltage.
The invention is not limited to the features and advantages described above. Other features are described below. The invention is defined by the appended claims.
Reference will now be made in detail to one or more embodiments of the invention. While the invention will be described with respect to these embodiments, it should be understood that the invention is not limited to any particular embodiment. On the contrary, the invention includes alternatives, modifications, and equivalents as may come within the spirit and scope of the appended claims. Furthermore, in the following description, numerous specific details are set forth to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known structures and principles of operation have not been described in detail to avoid obscuring the invention.
Turning now to
An exemplary self-bias generation circuit 305 is illustrated in
G(VP−VN)+ΔV=VP0−VN0
where G is the gain of the differential amplifier, VP and VN are the voltages at the input nodes P and N, respectively, and VP0 and VN0 are the voltages at the output nodes P0 and N0, respectively. Should VP0 equal VN and VN0 equal VP such as when the bias control signal is asserted, the preceding equation leads to:
ΔV/(G+1)=−(VP−VN)
As a result, the offset is reduced by the factor (G+1), Because the open loop gain G is large for a differential amplifier, the effect of the offset voltage is virtually eliminated. It will be appreciated that other topologies may be used for the self-bias generation circuit to eliminate the offset effect in this fashion.
Turning now to
A hybrid architecture for DRAM 500 will now be discussed. As known in the CMOS arts, a CMOS circuit may include input/output (I/O) transistors and core transistors. The I/O transistors are more robust than the core transistors so as to handle the relatively large voltages used in conventional I/O protocols. In contrast, the core transistors are smaller and cannot be subjected to the I/O voltages. Instead, the core transistors are powered using a core voltage that is lower than the I/O voltage used in the I/O transistors. For example, in modern high-density CMOS, the core voltage (which will be referred to herein as VDD) may be just 1V whereas the I/O voltage (which will be referred to herein as VIO) may be 2.5V. Advantageously, DRAM 500 is constructed from a mix of I/O and core transistors to maximize density and performance. The memory cells (discussed with regard to
Although the sense amplifier discussed with regard to
As a result, although a sense amplifier with self-bias generation advantageously is more sensitive to the voltage differences produced by accessing a memory cell, the self-bias generation may push the sense amplifier into having less than ideal margins between logical 0 and logical 1 decisions. Referring again to
As discussed with regard to
Each replica word line couples to a replica access transistor and a replica storage capacitor that are matched to the actual access transistors and storage capacitors. For example, word line We drives the gate of a replica access transistor 600 so that a replica storage capacitor 605 will be coupled to bit line Bx. To prevent stray charge from storage capacitor 605 undesirably affecting the voltage on bit line Bx, it has a terminal shorted to bit line Bx. Similarly, word line Wo drives the gate of a replica access transistor 610 so that a replica storage capacitor 615 is coupled to bit line B (for illustration clarity the replica word lines and associated circuitry for bit lines B′ and Bx′ are not shown). Consider the advantages of such a memory architecture—whatever access-transistor-capacitively-induced voltage increase that occurs when memory cells coupled to bit line B are being accessed, the same voltage increase will occur on bit line Bx, Similarly, if memory cells coupled to bit line Bx are being accessed, any access-transistor-capacitively-induced voltage increase on bit line Bx will also occur on bit line B. In this fashion, no voltage difference will be induced between the sensed bit lines despite the corresponding access transistors being driven on. Although the voltage difference is thus cancelled, both bit line voltages are now slightly increased in voltage from the offset-cancelling levels induced by the self-bias circuit. To bring the bit line voltage levels back to this ideal level, feedback transistors 405 and 410 (
After processing the voltages on nodes P and N, the bit lines will be pulled fill rail (in core voltage VDD) in a complementary fashion through the regenerative latching action of regenerative latch 320 (
Pre-charge circuit 310 may comprise NMOS transistors 710 and 715 that couple between a power supply of voltage VDD/2 and their respective bit lines. Prior to memory cell access, a controller (not illustrated) will drive transistors 710 and 715 on so that the bit line voltages are raised to VDD/2. A balance transistor 735 also conducts to ensure voltage equality between the bit lines. Transistors 710, 715, and 735 are then turned off so that the bit lines float during the self-bias cancellation process discussed previously. During this process, isolation transistors 725 and 730 are turned on to couple the respective bit lines to the self-bias generation circuit. After the offset bias is removed and the feedback transistors (
After sensing, sense amplifier 300 may be switched off as illustrated in
The combination of the offset bias cancellation and word line compensation discussed above leads to a very sensitive sense amplifier design. Because the sense amplifier may thus service more word line rows, density is dramatically improved. Moreover, the use of I/O voltages in the memory cells (which provides more charge to drive the bit lines) and also the bit line biasing during idle periods discussed with regard to
To keep the memory cells compatible with CMOS processes, the storage capacitors discussed with regard to
A node 905 of the storage capacitor is charged by the corresponding bit line. Node 905 includes metal layer plates or conductors coupled through vias 920. Node 905 is separated from an adjacent node 910 to form the capacitor. Node 910 may comprise corresponding metal layer plates coupled by vias as discussed with regard to node 905. In such an embodiment, node 910 would thus be tied to a desired voltage level such as ground. But as will explained further herein, a dramatic increase in capacitance may be achieved if signal-bearing conductors are used to form node 910. A resulting memory cell 1000 is illustrated in
An exemplary layout for metal-layer storage capacitor 1001 will now be discussed. Referring back to
The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.
Claims
1. A DRAM, comprising:
- a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a first node coupled to the access transistor and a second node isolated from the first node, the second node comprising signal-bearing metal conductors.
2. The DRAM of claim 1, wherein the DRAM is configured to drive at least one of the signal-bearing metal conductors to a supply voltage if the storage capacitor is being written with a ground voltage, and wherein the DRAM is configured to drive at least one of the signal-bearing metal conductors to ground if the storage capacitors is being written with a power supply voltage.
2. The DRAM of claim 1, wherein one of the signal-bearing metal conductors conducts a global read signal.
3. The DRAM of claim 2, wherein the storage capacitor is a trench capacitor.
4. The DRAM of claim 2, wherein the storage capacitor is a storage transistor.
5. The DRAM of claim 2, wherein the storage capacitor is a metal-layer capacitor.
6. The DRAM of claim 1, further comprising:
- a pair of bit lines, each bit line being couplable to selected ones of the memory cells;
- a differential amplifier adapted to amplify a voltage difference between the pair of bit lines; and
- a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.
7. The DRAM of claim 6, further comprising a regenerative latch that drives the pair of bit lines responsive to the amplification of the voltage difference.
8. The DRAM of claim 7, further comprising a first trim capacitor coupled to a first one of the bit lines and a second trim capacitor coupled to a second one of the bit lines.
9. The DRAM of claim 6, wherein the differential amplifier drives a pair of output nodes responsive to the voltage difference amplification between a pair of input nodes coupled to the bit lines, each of the input and output node pairs comprising a positive node and a negative node, and wherein the self-bias generation circuit comprises a first transistor that couples the positive input node to the negative output node and a second transistor that couples the negative input node to the positive output node.
10. The DRAM of claim 7, wherein the differential amplifier and regenerative latch are constructed using core transistors, and wherein the memory cells are constructed using I/O transistors.
11. The DRAM of claim 10, further comprising: a level-shifting circuit constructed from I/O transistors, the level-shifting circuit being operable to shift a core level output voltage from the regenerative latch into an I/O level voltage for driving the bit lines, the regenerative latch thereby driving a first one of the bit lines to the I/O level voltage and a remaining one of the bit lines to a ground voltage during a read/refresh operation.
12. The DRAM of claim 11, wherein the level-shifting circuit comprises cross-coupled PMOS transistors.
13. The DRAM of claim 12, wherein the level-shifting circuit further comprises isolation transistors inserted into the bit lines, the isolation transistors being driven with the core level voltage plus a threshold voltage during a read/refresh operation so as to divide each bit line into a first portion extending from the memory cells to the bit line's isolation transistor and into a second portion extending from the bit line's isolation transistor to the differential amplifier.
14. A method of operating a DRAM, wherein the DRAM includes a plurality of memory cells, each memory cell including a storage capacitor having a first terminal formed by signal-bearing conductors for the DRAM, the method comprising:
- writing a first binary value into a first one of the storage capacitors by grounding a second opposing terminal of the storage capacitor while charging at least one of the signal-bearing conductors that form the first terminal to a power supply voltage; and
- writing a second binary value into a second one of the storage capacitors by charging a second opposing terminal of the storage capacitor while grounding at least one of the signal-bearing conductors that form the first terminal.
15. The method of claim 14, further comprising:
- reading the binary value written into the first one of the storage capacitors while charging the at least one of the signal-bearing conductors that form the first plate to the power supply voltage.
16. The method of claim 16, further comprising:
- reading the binary value written into the second one of the storage capacitors while charging the at least one of the signal-bearing conductors that form the first plate to the power supply voltage.
17. The method of claim 14, wherein the power supply voltage is an I/O-level voltage.
18. A DRAM, comprising:
- a plurality of memory cells, each memory cell including a storage capacitor having a first terminal coupled to an access transistor and a second terminal coupled to at least one signal-bearing conductor for the DRAM, wherein the DRAM is configured to charge the at least one signal-bearing conductor to a power supply voltage if the DRAM is writing a binary value into the memory cell such that the first terminal is grounded, and wherein the DRAM is further configured to ground the at least one signal-bearing conductor if the DRAM is writing a binary value into the memory cell such that the first terminal is charged to a power supply voltage.
19. The DRAM of claim 18, wherein the storage capacitors are metal-layer capacitors.
20. The DRAM of claim 18, wherein the storage capacitors are storage transistors.
Type: Application
Filed: Aug 27, 2007
Publication Date: Oct 30, 2008
Inventors: Esin Terzioglu (Aliso Viejo, CA), Gil I. Winograd (Aliso Viejo, CA), Morteza Cyrus Afghahi (Coto De Caza, CA)
Application Number: 11/845,349
International Classification: G11C 11/24 (20060101); G11C 7/10 (20060101);