METHOD OF MANUFACTURING NON-VOLATILE MEMORY
A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric layer is formed on the sidewall of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. An epitaxy layer is formed on the substrate between two first gate structures. A third dielectric layer is formed on the epitaxy layer. A second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are removed to form second gate structures. Finally, a doped region is formed in the substrate at two sides of the second gate structures.
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This application claims the priority benefit of Taiwan application serial no. 96129848, filed on Aug. 13, 2007. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a non-volatile memory.
2. Description of Related Art
A memory is a semiconductor device designed to store information or data. With the production of increasingly powerful microprocessors in computers, programs and calculations that are executed by software expand significantly. As a result, demands for high storage capacity memories increase correspondingly. An incentive to produce the memory with high storage capacity and low costs in order to satisfy the aforesaid requirements has now motivated semiconductor manufacturers to fabricate memory devices with great integrity.
Among various types of memory products, a non-volatile memory allows multiple data writing, reading and erasing operations. The stored data will be retained even after power to the memory device is removed. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipment.
In general, during the fabrication of the non-volatile memory, the tunneling dielectric layers 112 and the floating gates 114 disposed thereon are formed on the substrate 100 at first. Thereafter, the inter-gate dielectric layers 118, the gate dielectric layer 106, the control gate 108 and other components are sequentially formed between the floating gates 114.
However, because the gate dielectric layer 106 is usually formed by thermal oxidation the gate dielectric layer 106 is not only formed on the substrate 100 between the floating gates 114 but also extended below the floating gates 114, such that a bird's beak effect occurs. Thereby, a thickness of each of the tunneling dielectric layers 112 is increased, giving rise to an unsatisfactory movement of electrons during an operation of the non-volatile memory and reducing the work efficiency of the non-volatile memory.
On the other hand, with an increase of integrity, dimensions of the devices are continuously reduced. Besides, the spacer is usually formed between the floating gates and the control gate to prevent the bird's beak effect. Both of which arise from a short channel effect due to an insufficient channel length.
SUMMARY OF THE INVENTIONIn view of the foregoing, the present invention is directed to a method of manufacturing a non-volatile memory to prevent a bird's beak effect, and to resolve the issue regarding an increased thickness of a tunneling dielectric layer, and avoid a short channel effect.
The present invention provides a method of manufacturing a non-volatile memory. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are then patterned to form a plurality of first gate structures. A second dielectric layer is then formed on sidewalls of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. Thereafter, an epitaxy layer is formed on the substrate between two adjacent first gate structures. Next, a third dielectric layer is formed on the epitaxy layer. Afterwards, a second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are then removed to form a plurality of second gate structures. Finally, a doped region is formed in the substrate at two sides of each of the second gate structures.
According to an embodiment of the present invention, a thickness of the epitaxy layer ranges from 200 Å to 300 Å, for example.
According to an embodiment of the present invention, the epitaxy layer is formed by performing a selective-epi growth (SEG) process, for example.
According to an embodiment of the present invention, the epitaxy layer is an epitaxial silicon layer, for example.
According to an embodiment of the present invention, after the second conductive layer is formed but before the first cap layer and a portion of the first conductive layer are removed, a portion of the second conductive layer is removed. Next, an oxidation process is performed on the residual second conductive layer, so as to form a second cap layer on the second conductive layer.
According to an embodiment of the present invention, the step of forming the second gate structures further comprises performing a first oxidation process on the first conductive layer and forming a spacer on the sidewall of the second conductive layer after removing the first cap layer but before removing a portion of the first conductive layer Next, a portion of the first conductive layer is removed with use of the spacer as a mask. After that, a second oxidation process is performed on the residual first conductive layer.
According to an embodiment of the present invention, a material of the spacer is silicon nitride, for example.
According to an embodiment of the present invention, the doped region is formed by performing an ion implantation process, for example.
According to an embodiment of the present invention, a material of the first conductive layer is doped polysilicon, for example.
According to an embodiment of the present invention, a material of the second conductive layer is doped polysilicon, for example.
According to an embodiment of the present invention, the step of forming the second dielectric layer and removing a portion of the first dielectric layer includes forming a dielectric material layer conformally on the substrate at first. Thereafter, a dry etching process is implemented.
In the present invention, before the dielectric layer serving as a gate dielectric layer is formed by thermal oxidation, the epitaxy layer is formed on the substrate, and the dielectric layer is then formed on the epitaxy layer. Thereby, the dielectric layer can be avoided from being expended below the first gate structures during thermal oxidation, thus avoiding the occurrence of the bird's beak effect. Moreover, through the epitaxy layer disposed on the substrate, a channel length is increased, and shortcomings associated with the short channel effect are then overcome.
In order to make the aforementioned and other objects, features and advantages of the present invention more comprehensible, an embodiment accompanied with figures is described in detail below.
First, referring to
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After that, referring to
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To sum up, in the present invention, before the gate dielectric layer disposed below the control gate is formed by thermal oxidation, the epitaxy layer is formed on the substrate, and the gate dielectric layer is then formed on the epitaxy layer. Thereby, the gate dielectric layer is avoided from being extended below the tunneling dielectric layer during thermal oxidation, and no bird's beak phenomenon takes place. Besides, the thickness of the tunneling dielectric layer is prevented from increasing and adversely affecting performance of the device.
Furthermore, the formation of the epitaxy layer on the substrate contributes to the increase in the channel length, thus avoiding the short channel effect.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1. A method of manufacturing a non-volatile memory, the method comprising:
- forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate;
- patterning the first cap layer, and the first conductive layer to form a plurality of first gate structures;
- forming a second dielectric layer on sidewalls of the first gate structures and removing a portion of the first dielectric layer to expose an area of the substrate between the two adjacent first gate structures;
- forming an epitaxy layer on the substrate between the two adjacent first gate structures;
- forming a third dielectric layer on the epitaxy layer;
- forming a second conductive layer on the third dielectric layer;
- removing the first cap layer and a portion of the first conductive layer to form a plurality of second gate structures; and
- forming a doped region in the substrate at two sides of the second gate structures.
2. The method of claim 1, wherein a thickness of the epitaxy layer ranges from 200 Å to 300 Å.
3. The method of claim 1, wherein the step of forming the epitaxy layer comprises performing a selective-epi growth (SEG) process.
4. The method of claim 1, wherein the epitaxy layer comprises an epitaxial silicon layer.
5. The method of claim 1, wherein after the second conductive layer is formed but before the first cap layer and a portion of the first conductive layer are removed, the method further comprises:
- removing a portion of the second conductive layer; and
- performing an oxidation process on the residual second conductive layer, such that a second cap layer is formed on the second conductive layer.
6. The method of claim 1, wherein the step of forming the second gate structures further comprises:
- performing a first oxidation process on the first conductive layer and forming a spacer on the sidewall of the second conductive layer after removing the first cap layer and before removing a portion of the first conductive layer;
- removing a portion of the first conductive layer with use of the spacer as a mask; and
- performing a second oxidation process on the residual first conductive layer.
7. The method of claim 6, wherein a material of the spacer comprises silicon nitride.
8. The method of claim 7, wherein the step of forming the doped region comprises performing an ion implantation process.
9. The method of claim 8, wherein a material of the first conductive layer comprises doped polysilicon.
10. The method of claim 6, wherein a material of the second conductive layer comprises doped polysilicon.
11. The method of claim 6, wherein the step of forming the second dielectric layer and removing a portion of the first dielectric layer comprises:
- conformlly forming a dielectric material layer on the substrate; and
- performing a dry etching process.
Type: Application
Filed: Dec 13, 2007
Publication Date: Feb 19, 2009
Applicant: NANYA TECHNOLOGY CORPORATION (Taoyuan)
Inventors: Hung-Mine Tsai (Kaohsiung City), Ching-Nan Hsiao (Kaohsiung County), Chung-Lin Huang (Taoyuan County)
Application Number: 11/955,393
International Classification: H01L 21/336 (20060101);