With Floating Gate (epo) Patents (Class 257/E21.422)
  • Patent number: 11908889
    Abstract: Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 20, 2024
    Assignee: SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.
    Inventors: Yi Gong, Wei Liu, Yuanlin Yuan, Lei Liu, Rui Wang
  • Patent number: 11810616
    Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: November 7, 2023
    Assignee: Infineon Technologies LLC
    Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
  • Patent number: 11810983
    Abstract: Provided is a semiconductor device including a substrate, a tunneling insulating film disposed on the substrate, a control gate electrode disposed on the tunneling insulating film, a first floating gate electrode disposed between the control gate electrode and the tunneling insulating film, a second floating gate electrode disposed between the first floating gate electrode and the tunneling insulating film, a first control gate insulating film disposed between the first floating gate electrode and the control gate electrode, a second control gate insulating film disposed between the second floating gate electrode and the first floating gate electrode, and a source electrode and a drain electrode disposed on the substrate to be spaced apart from each other with respect to the control gate electrode, wherein the control gate electrode includes a first metal material, wherein the first floating gate electrode includes a second metal material, wherein the second floating gate electrode includes a third metal mate
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: November 7, 2023
    Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventor: Tae Sik Yoon
  • Patent number: 11737258
    Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: August 22, 2023
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 11696433
    Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: July 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Fredrick Fishburn
  • Patent number: 11695050
    Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Ramanathan Gandhi
  • Patent number: 11658248
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Yi-Ling Liu, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
  • Patent number: 11637187
    Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: April 25, 2023
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Heng Liu, Zhigang Yang, Jianghua Leng, Tianpeng Guan
  • Patent number: 11631772
    Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 18, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Thomas Melde, Stefan Dünkel, Ralf Richter
  • Patent number: 11594620
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 11527630
    Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Pin Chang, Chien-Hung Liu, Chih-Wei Hung
  • Patent number: 11476334
    Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Orb Acton, Joseph Steigerwald, Anand Murthy, Scott Maddox, Jenny Hu
  • Patent number: 11386963
    Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: July 12, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11342421
    Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: May 24, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kung-Ming Fan
  • Patent number: 11239312
    Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 1, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Hideaki Tsuchiko
  • Patent number: 11161281
    Abstract: A capacitive sensor array for in-situ monitoring directed self-assembly of a self-assembling material is provided. The capacitive sensor array includes a bottom electrode plate including a plurality of bottom electrodes that are spaced apart and electrically isolated from one another, template structures located on the bottom electrode plate, wherein the template structures define trenches therebetween, each of the trenches exposing at least one of the plurality of bottom electrodes; and a top electrode plate assembled on the bottom electrode plate, wherein the top electrode plate includes a plurality of top electrodes that are spaced apart and electrically isolated from one another, the top electrodes facing and intersecting, but electrically isolated from, the bottom electrodes.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Frank R. Libsch, Venkat K. Balagurusamy
  • Patent number: 11164946
    Abstract: A manufacturing method for a flash device. A manufacturing method for a flash device, comprising: providing a substrate; forming sequentially, on the substrate, a floating gate (FG) oxide layer, an FG polycrystalline layer, and an FG mask layer; etching, at the FG location region, the FG polycrystalline layer and the FG mask layer, forming a window on the FG mask layer, and forming a trench on the FG polycrystalline layer, the window being communicated with the trench; performing second etching of the side wall of the window of the FG mask layer, enabling the width of the trench located on the FG polycrystalline layer to be less than the width of the secondarily-etched window located on the FG mask layer; and oxidizing the FG polycrystalline layer, enabling the oxide to fill the trench to form a field oxide layer; and etching an FG having sharp angles.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 2, 2021
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Tao Liu, Zhibin Liang, Song Zhang, Yan Jin, Dejin Wang
  • Patent number: 10559364
    Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Futatsuyama, Kenichi Abe
  • Patent number: 10424589
    Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: September 24, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: James Walls, Mel Hymas, Sajid Kabeer
  • Patent number: 10340013
    Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Futatsuyama, Kenichi Abe
  • Patent number: 10318071
    Abstract: A method and apparatus for generating touch blob angle orientation in a touch device are described. In one embodiment, the apparatus comprises a touch processing unit operable to analyze sensor data generated from touch inputs on a touchscreen and generate touch blob information for each detected touch blob; and a filter coupled to the touch processing unit operable to filter blob orientation information from a filter output in response to detection of a finger lifting event.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 11, 2019
    Assignee: INTEL CORPORATION
    Inventors: Nobuyuki Suzuki, Dale Bengtson, Vijay Venkatesh Mahalingam, Lee Nau
  • Patent number: 10170327
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 10026820
    Abstract: A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 17, 2018
    Assignee: NXP USA, Inc.
    Inventors: Weize Chen, Cheong Min Hong, Konstantin V. Loiko, Jane A. Yater
  • Patent number: 9900007
    Abstract: An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Tatsuji Nishijima
  • Patent number: 9847397
    Abstract: A first doped region extends from a top surface of a substrate to a first depth. An implant into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 19, 2017
    Assignee: NXP USA, Inc.
    Inventors: Cheong Min Hong, Konstantin V. Loiko, Jane A. Yater
  • Patent number: 9780107
    Abstract: Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Umberto M. Meotto, Giulio Albini, Paolo Tessariol, Paola Bacciaglia, Marcello Mariani
  • Patent number: 9691776
    Abstract: A nonvolatile memory device may include: an isolation layer formed in a substrate and defining an active region; a control plug formed over the isolation layer; a floating gate formed over the substrate and including a plurality of fingers adjacent to the control plug with a gap provided therebetween; and a charge blocking layer formed on sidewalls of the floating gate so as to fill the gap. The control plug may include: a first control plug formed between the plurality of fingers and having sidewalls facing inner walls of the fingers; and a second control plug formed outside the floating gate and having sidewalls facing outer walls of the fingers.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventor: Sung-Kun Park
  • Patent number: 9627068
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9601568
    Abstract: Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 21, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 9570457
    Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chiang Min, Tsung-Hsueh Yang, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 9514945
    Abstract: A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Euhngi Lee
  • Patent number: 9496417
    Abstract: A non-volatile memory cell includes a tunneling part; a coupling device; a read transistor; a first select transistor connected to the read transistor forming a read path with the read transistor in a read mode; an erase tunneling structure forming a tunneling ejection path in an erase mode; and a program tunneling structure forming a tunneling injection path in an program mode; wherein the read path is different from the tunneling ejection path and the tunneling injection path.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: November 15, 2016
    Assignee: AMIC Technology Corporation
    Inventors: Hsiao-Hua Lu, Chih-Ming Kuo, Chih-Lung Chang
  • Patent number: 9431257
    Abstract: An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates. A silicide contact pad is arranged over a top surface of the first memory cell gate. The silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate. A method of manufacturing the integrated circuit is also provided.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ming Chyi Liu
  • Patent number: 9425044
    Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsing Chang, Ming Chyi Liu, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 9401694
    Abstract: An operational transconductance amplifier includes a fully-differential amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The fully-differential amplifying circuit is configured for receiving a differential input voltage and providing a differential output voltage. The fully-differential amplifying circuit includes a plurality of diffusor-differential-pair circuits. The bias driving circuit is configured for providing at least one first bias current to drive the fully-differential amplifying circuit and adjust the transconductance of the transconductance amplifier. The common mode feedback circuit is configured for stabilizing the differential output voltage. An operational transconductance amplifier-capacitor (OTA-C) filter and a high order filter are disclosed herein as well.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: July 26, 2016
    Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Sheng-Yu Peng, Hung-Yu Shih, Min-Rui Lai, Chiang-His Lee, Tzu-Yun Wang
  • Patent number: 9034698
    Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Ozu, Shota Yoshimura, Hiroto Ohtake, Kosuke Kariu, Takashi Tsukamoto
  • Patent number: 8981455
    Abstract: In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Aoyama
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Patent number: 8962416
    Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Konstantin V. Loiko, Jane A. Yater
  • Patent number: 8946806
    Abstract: A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.
    Type: Grant
    Filed: July 24, 2011
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Eng Huat Toh, Elgin Quek, Yanzhe Tang
  • Patent number: 8936983
    Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Kang Jae Lee, Eun Joo Jung
  • Patent number: 8933501
    Abstract: A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 13, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee
  • Patent number: 8921915
    Abstract: A nonvolatile memory device includes a multi-finger type control gate formed over a substrate, a multi-finger type floating gate formed over the substrate and disposed close to the control gate with gaps defined therebetween, and spacers formed on sidewalls of the control gate and the floating gate, and filling the gaps.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sung-Kun Park
  • Patent number: 8921922
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
  • Patent number: 8906764
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8901632
    Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater
  • Patent number: 8896048
    Abstract: The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: November 25, 2014
    Assignee: Spansion LLC
    Inventors: Richard Fastow, Zhigang Wang, Yue-Song He, Kazuhiro Mizutani, Pavel Fastenko
  • Patent number: 8895390
    Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8890230
    Abstract: A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.
    Type: Grant
    Filed: July 15, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Hsu, Chi Ren, Tzeng-Fei Wen
  • Patent number: 8878282
    Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshitake Yaegashi